mirror of
https://github.com/zephyrproject-rtos/zephyr
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342cbc9e01
Add LiteX with softcore CPU VexRiscV SoC definitions and default configurations. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com> |
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| .. | ||
| microsemi-miv.dtsi | ||
| riscv32-fe310.dtsi | ||
| riscv32-litex-vexriscv.dtsi | ||
| rv32m1_ri5cy.dtsi | ||
| rv32m1_zero_riscy.dtsi | ||
| rv32m1.dtsi | ||