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https://github.com/zephyrproject-rtos/zephyr
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a7b54980bd
Nios II CPUs vary in configuration on whether they support 'mul', 'mulx', and 'div' family of instructions. The compiler can be told to use GCC integer library routines instead if needed. Ideally we would just pull the configuration out of system.h, but pulling include file #defines into the Make environment will involve some build system work that is best left to a later improvement. We've decided to take this build-time approach rather than handle unimplemented instruction exceptions, so remove the hook in exception.S Change-Id: I05be0d5ed4c1a49b23dca1550ee66fd5891044d2 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
247 lines
6.6 KiB
ArmAsm
247 lines
6.6 KiB
ArmAsm
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define _ASMLANGUAGE
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#include <arch/nios2/asm.h>
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#include <nano_private.h>
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/* exports */
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GTEXT(_exception)
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GTEXT(_exception_exit)
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GTEXT(_exception_enter_fault)
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/* import */
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GTEXT(_Fault)
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GTEXT(_Swap)
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#ifdef CONFIG_IRQ_OFFLOAD
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GTEXT(_irq_do_offload)
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GTEXT(_offload_routine)
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#endif
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/* Allows use of r1/at register, otherwise reserved for assembler use */
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.set noat
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/* Placed into special 'exception' section so that the linker can put this code
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* at ALT_CPU_EXCEPTION_ADDR defined in system.h
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*
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* This is the common entry point for processor exceptions and interrupts from
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* the Internal Interrupt Controller (IIC).
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*
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* If the External (EIC) controller is in use, then we will never get here on
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* behalf of an interrupt, instead the EIC driver will have set up a vector
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* table and the processor will jump directly into the appropriate table
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* entry.
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*/
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SECTION_FUNC(exception.entry, _exception)
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/* Reserve thread stack space for saving context */
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addi sp, sp, -76
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/* Preserve all caller-saved registers onto the thread's stack */
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stw ra, 0(sp)
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/* Gap here for muldiv handler to store zero register */
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stw r1, 8(sp)
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stw r2, 12(sp)
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stw r3, 16(sp)
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stw r4, 20(sp)
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stw r5, 24(sp)
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stw r6, 28(sp)
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stw r7, 32(sp)
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stw r8, 36(sp)
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stw r9, 40(sp)
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stw r10, 44(sp)
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stw r11, 48(sp)
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stw r12, 52(sp)
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stw r13, 56(sp)
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stw r14, 60(sp)
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stw r15, 64(sp)
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/* Store value of estatus control register */
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rdctl et, estatus
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stw et, 68(sp)
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/* ea-4 is the address of the instruction when the exception happened,
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* put this in the stack frame as well
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*/
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addi r15, ea, -4
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stw r15, 72(sp)
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/* Figure out whether we are here because of an interrupt or an
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* exception. If an interrupt, switch stacks and enter IRQ handling
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* code. If an exception, remain on current stack and enter exception
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* handing code. From the CPU manual, ipending must be nonzero and
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* estatis.PIE must be enabled for this to be considered an interrupt.
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*
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* Stick ipending in r4 since it will be an arg for _enter_irq
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*/
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rdctl r4, ipending
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beq r4, zero, not_interrupt
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/* We stashed estatus in et earlier */
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andi r15, et, 1
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beq r15, zero, not_interrupt
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BRANCH_LABEL(is_interrupt)
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/* If we get here, this is an interrupt */
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/* Grab a reference to _nanokernel in r10 so we can determine the
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* current irq stack pointer
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*/
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movhi r10, %hi(_nanokernel)
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ori r10, r10, %lo(_nanokernel)
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/* Stash a copy of thread's sp in r12 so that we can put it on the IRQ
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* stack
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*/
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mov r12, sp
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/* Switch to interrupt stack */
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ldw sp, __tNANO_irq_sp_OFFSET(r10)
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/* Store thread stack pointer onto IRQ stack */
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addi sp, sp, -4
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stw r12, 0(sp)
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BRANCH_LABEL(on_irq_stack)
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/* Enter C interrupt handling code. Value of ipending will be the
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* function parameter since we put it in r4
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*/
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call _enter_irq
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/* Interrupt handler finished and the interrupt should be serviced
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* now, the appropriate bits in ipending should be cleared */
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/* Get a reference to _nanokernel again in r10 */
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movhi r10, %hi(_nanokernel)
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ori r10, r10, %lo(_nanokernel)
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/* Determine whether the execution of the ISR requires a context
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* switch. If the interrupted thread is PREEMPTIBLE (a task) and
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* _nanokernel.fiber is non-NULL, a _Swap() needs to occur.
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*/
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/* Check (_nanokernel.current->flags & PREEMPTIBLE), if not
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* goto no_reschedule
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*/
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ldw r11, __tNANO_current_OFFSET(r10)
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ldw r12, __tTCS_flags_OFFSET(r11)
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movi r13, PREEMPTIBLE
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and r12, r13, r12
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beq r12, zero, no_reschedule
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/* Check _nanokernel.fiber != NULL, if NULL goto no_reschedule */
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ldw r11, __tNANO_fiber_OFFSET(r10)
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beq r11, zero, no_reschedule
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/*
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* A context reschedule is required: keep the volatile registers of
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* the interrupted thread on the context's stack. Utilize
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* the existing _Swap() primitive to save the remaining
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* thread's registers (including floating point) and perform
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* a switch to the new thread.
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*/
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/* We put the thread stack pointer on top of the IRQ stack before
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* we switched stacks. Restore it to go back to thread stack
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*/
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ldw sp, 0(sp)
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/* Argument to Swap() is estatus since that's the state of the
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* status register before the exception happened. When coming
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* out of the context switch we need this info to restore
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* IRQ lock state. We put this value in et earlier.
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*/
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mov r4, et
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call _Swap
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jmpi _exception_exit
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BRANCH_LABEL(not_interrupt)
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/* Since this wasn't an interrupt we're not going to restart the
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* faulting instruction. If it's an unimplemented math instruction,
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* the muldiv code will handle it, else we just give up and _Fault.
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*
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* We earlier put ea - 4 in the stack frame, replace it with just ea
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*/
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stw ea, 72(sp)
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#ifdef CONFIG_IRQ_OFFLOAD
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/* Check the contents of _offload_routine. If non-NULL, jump into
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* the interrupt code anyway.
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*/
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movhi r10, %hi(_offload_routine)
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ori r10, r10, %lo(_offload_routine)
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ldw r11, (r10)
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bne r11, zero, is_interrupt
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#endif
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SECTION_FUNC(exception.entry, _exception_enter_fault)
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/* If we get here, the exception wasn't in interrupt or an
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* unimplemented math instruction. Let _Fault() handle it in
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* C domain
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*/
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ldw r4, 0(sp)
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call _Fault
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jmpi _exception_exit
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BRANCH_LABEL(no_reschedule)
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/* We put the thread stack pointer on top of the IRQ stack before
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* we switched stacks. Restore it to go back to thread stack
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*/
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ldw sp, 0(sp)
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/* Fall through */
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SECTION_FUNC(exception.entry, _exception_exit)
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/* We are on the thread stack. Restore all saved registers
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* and return to the interrupted context */
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/* Return address from the exception */
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ldw ea, 72(sp)
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/* Restore estatus
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* XXX is this right??? */
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ldw r5, 68(sp)
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wrctl estatus, r5
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/* Restore caller-saved registers */
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ldw ra, 0(sp)
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ldw r1, 8(sp)
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ldw r2, 12(sp)
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ldw r3, 16(sp)
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ldw r4, 20(sp)
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ldw r5, 24(sp)
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ldw r6, 28(sp)
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ldw r7, 32(sp)
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ldw r8, 36(sp)
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ldw r9, 40(sp)
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ldw r10, 44(sp)
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ldw r11, 48(sp)
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ldw r12, 52(sp)
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ldw r13, 56(sp)
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ldw r14, 60(sp)
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ldw r15, 64(sp)
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/* Put the stack pointer back where it was when we entered
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* exception state
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*/
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addi sp, sp, 76
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/* All done, copy estatus into status and transfer to ea */
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eret
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