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zephyr/arch
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Andrew Boie edc5e31d6b x86_64: fix RBX clobber in nested IRQ case 
In the code path for nested interrupts, we are not saving
RBX, yet the assembly code is using it as a storage location
for the ISR.

Use RAX. It is backed up in both the nested and non-nested
cases, and the ASM code is not currently using it at that
point.

Fixes: #29594

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2020-10-28 10:29:32 -07:00
..
arc arc: cpu_idle: remove sleep workround for nsim_hs_smp 2020-10-22 06:17:08 -04:00
arm arm: cortex_m: add support for thread local storage 2020-10-24 10:52:00 -07:00
common
nios2
posix arch: posix: add missing include for cpuhalt.c 2020-10-20 08:54:59 +02:00
riscv riscv: add support for thread local storage 2020-10-24 10:52:00 -07:00
x86 x86_64: fix RBX clobber in nested IRQ case 2020-10-28 10:29:32 -07:00
xtensa xtensa: add support for thread local storage 2020-10-24 10:52:00 -07:00
CMakeLists.txt
Kconfig riscv: add support for thread local storage 2020-10-24 10:52:00 -07:00