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LPC GPIO architecture uses multiple devices. GPIO input is routed via INPUTMUX to the PINT device which roots the interrupt to NVIC. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
38 lines
711 B
Plaintext
38 lines
711 B
Plaintext
# MCUX LPC GPIO configuration options
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# Copyright (c) 2017, NXP
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# SPDX-License-Identifier: Apache-2.0
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menuconfig GPIO_MCUX_LPC
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bool "MCUX LPC GPIO driver"
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depends on HAS_MCUX
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select HAS_DTS_GPIO
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help
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Enable the MCUX LPC pinmux driver.
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if GPIO_MCUX_LPC
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config GPIO_MCUX_LPC_PORT0
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bool "Port 0"
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depends on PINMUX_MCUX_LPC_PORT0
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help
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Enable Port 0.
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config GPIO_MCUX_LPC_PORT0_NAME
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string "Port 0 driver name"
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depends on GPIO_MCUX_LPC_PORT0
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default "GPIO_0"
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config GPIO_MCUX_LPC_PORT1
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bool "Port 1"
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depends on PINMUX_MCUX_LPC_PORT1
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help
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Enable Port 1.
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config GPIO_MCUX_LPC_PORT1_NAME
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string "Port 1 driver name"
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depends on GPIO_MCUX_LPC_PORT1
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default "GPIO_1"
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endif # GPIO_MCUX_LPC
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