mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-13 13:35:21 +00:00
064f5f0cef
It needs to verify if the callback was not already installed, and if so: if is was in controller's list. It should return an error in case the node is not found though it was requested to be removed. If already inserted, it will be silently removed but added again, to avoid circular list as stated in the bug. Fixes #11394 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
410 lines
10 KiB
C
410 lines
10 KiB
C
/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <gpio.h>
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#include <soc.h>
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#include <gpio_imx.h>
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#include "gpio_utils.h"
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struct imx_gpio_config {
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GPIO_Type *base;
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};
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struct imx_gpio_data {
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/* port ISR callback routine address */
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sys_slist_t callbacks;
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/* pin callback routine enable flags, by pin number */
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u32_t pin_callback_enables;
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};
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static int imx_gpio_configure(struct device *dev,
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int access_op, u32_t pin, int flags)
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{
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const struct imx_gpio_config *config = dev->config->config_info;
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gpio_init_config_t pin_config;
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bool double_edge = false;
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u32_t i;
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/* Check for an invalid pin configuration */
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if ((flags & GPIO_INT) && (flags & GPIO_DIR_OUT)) {
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return -EINVAL;
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}
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pin_config.direction = ((flags & GPIO_DIR_MASK) == GPIO_DIR_IN)
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? gpioDigitalInput : gpioDigitalOutput;
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_EDGE) {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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pin_config.interruptMode = gpioIntRisingEdge;
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} else if (flags & GPIO_INT_DOUBLE_EDGE) {
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pin_config.interruptMode = gpioNoIntmode;
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double_edge = true;
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} else {
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pin_config.interruptMode = gpioIntFallingEdge;
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}
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} else { /* GPIO_INT_LEVEL */
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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pin_config.interruptMode = gpioIntHighLevel;
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} else {
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pin_config.interruptMode = gpioIntLowLevel;
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}
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}
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} else {
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pin_config.interruptMode = gpioNoIntmode;
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}
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if (access_op == GPIO_ACCESS_BY_PIN) {
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pin_config.pin = pin;
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GPIO_Init(config->base, &pin_config);
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GPIO_SetIntEdgeSelect(config->base, pin, double_edge);
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} else { /* GPIO_ACCESS_BY_PORT */
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for (i = 0U; i < 32; i++) {
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pin_config.pin = i;
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GPIO_Init(config->base, &pin_config);
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GPIO_SetIntEdgeSelect(config->base, i, double_edge);
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}
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}
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return 0;
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}
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static int imx_gpio_write(struct device *dev,
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int access_op, u32_t pin, u32_t value)
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{
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const struct imx_gpio_config *config = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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GPIO_WritePinOutput(config->base, pin,
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(gpio_pin_action_t)value);
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} else { /* GPIO_ACCESS_BY_PORT */
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GPIO_WritePortOutput(config->base, value);
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}
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return 0;
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}
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static int imx_gpio_read(struct device *dev,
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int access_op, u32_t pin, u32_t *value)
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{
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const struct imx_gpio_config *config = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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*value = GPIO_ReadPinInput(config->base, pin);
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} else { /* GPIO_ACCESS_BY_PORT */
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*value = GPIO_ReadPortInput(config->base);
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}
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return 0;
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}
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static int imx_gpio_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct imx_gpio_data *data = dev->driver_data;
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return _gpio_manage_callback(&data->callbacks, callback, set);
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}
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static int imx_gpio_enable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct imx_gpio_config *config = dev->config->config_info;
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struct imx_gpio_data *data = dev->driver_data;
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u32_t i;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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data->pin_callback_enables |= BIT(pin);
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GPIO_SetPinIntMode(config->base, pin, true);
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} else {
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data->pin_callback_enables = 0xFFFFFFFF;
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for (i = 0U; i < 32; i++) {
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GPIO_SetPinIntMode(config->base, i, true);
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}
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}
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return 0;
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}
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static int imx_gpio_disable_callback(struct device *dev,
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int access_op, u32_t pin)
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{
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const struct imx_gpio_config *config = dev->config->config_info;
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struct imx_gpio_data *data = dev->driver_data;
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u32_t i;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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GPIO_SetPinIntMode(config->base, pin, false);
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data->pin_callback_enables &= ~BIT(pin);
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} else {
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for (i = 0U; i < 32; i++) {
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GPIO_SetPinIntMode(config->base, i, false);
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}
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data->pin_callback_enables = 0U;
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}
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return 0;
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}
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static void imx_gpio_port_isr(void *arg)
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{
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struct device *dev = (struct device *)arg;
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const struct imx_gpio_config *config = dev->config->config_info;
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struct imx_gpio_data *data = dev->driver_data;
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u32_t enabled_int;
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u32_t int_flags;
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int_flags = GPIO_ISR_REG(config->base);
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enabled_int = int_flags & data->pin_callback_enables;
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_gpio_fire_callbacks(&data->callbacks, dev, enabled_int);
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GPIO_ISR_REG(config->base) = enabled_int;
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}
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static const struct gpio_driver_api imx_gpio_driver_api = {
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.config = imx_gpio_configure,
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.write = imx_gpio_write,
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.read = imx_gpio_read,
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.manage_callback = imx_gpio_manage_callback,
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.enable_callback = imx_gpio_enable_callback,
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.disable_callback = imx_gpio_disable_callback,
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};
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#ifdef CONFIG_GPIO_IMX_PORT_1
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static int imx_gpio_1_init(struct device *dev);
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static const struct imx_gpio_config imx_gpio_1_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_1_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_1_data;
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DEVICE_AND_API_INIT(imx_gpio_1, DT_GPIO_IMX_PORT_1_NAME,
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imx_gpio_1_init,
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&imx_gpio_1_data, &imx_gpio_1_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_1_init(struct device *dev)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_0,
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DT_GPIO_IMX_PORT_1_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0);
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irq_enable(DT_GPIO_IMX_PORT_1_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_1_IRQ_1,
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DT_GPIO_IMX_PORT_1_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_1), 0);
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irq_enable(DT_GPIO_IMX_PORT_1_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_1 */
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#ifdef CONFIG_GPIO_IMX_PORT_2
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static int imx_gpio_2_init(struct device *dev);
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static const struct imx_gpio_config imx_gpio_2_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_2_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_2_data;
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DEVICE_AND_API_INIT(imx_gpio_2, DT_GPIO_IMX_PORT_2_NAME,
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imx_gpio_2_init,
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&imx_gpio_2_data, &imx_gpio_2_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_2_init(struct device *dev)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_0,
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DT_GPIO_IMX_PORT_2_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0);
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irq_enable(DT_GPIO_IMX_PORT_2_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_2_IRQ_1,
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DT_GPIO_IMX_PORT_2_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_2), 0);
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irq_enable(DT_GPIO_IMX_PORT_2_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_2 */
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#ifdef CONFIG_GPIO_IMX_PORT_3
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static int imx_gpio_3_init(struct device *dev);
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static const struct imx_gpio_config imx_gpio_3_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_3_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_3_data;
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DEVICE_AND_API_INIT(imx_gpio_3, DT_GPIO_IMX_PORT_3_NAME,
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imx_gpio_3_init,
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&imx_gpio_3_data, &imx_gpio_3_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_3_init(struct device *dev)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_0,
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DT_GPIO_IMX_PORT_3_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0);
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irq_enable(DT_GPIO_IMX_PORT_3_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_3_IRQ_1,
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DT_GPIO_IMX_PORT_3_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_3), 0);
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irq_enable(DT_GPIO_IMX_PORT_3_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_3 */
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#ifdef CONFIG_GPIO_IMX_PORT_4
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static int imx_gpio_4_init(struct device *dev);
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static const struct imx_gpio_config imx_gpio_4_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_4_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_4_data;
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DEVICE_AND_API_INIT(imx_gpio_4, DT_GPIO_IMX_PORT_4_NAME,
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imx_gpio_4_init,
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&imx_gpio_4_data, &imx_gpio_4_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_4_init(struct device *dev)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_0,
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DT_GPIO_IMX_PORT_4_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0);
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irq_enable(DT_GPIO_IMX_PORT_4_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_4_IRQ_1,
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DT_GPIO_IMX_PORT_4_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_4), 0);
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irq_enable(DT_GPIO_IMX_PORT_4_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_4 */
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#ifdef CONFIG_GPIO_IMX_PORT_5
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static int imx_gpio_5_init(struct device *dev);
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static const struct imx_gpio_config imx_gpio_5_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_5_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_5_data;
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DEVICE_AND_API_INIT(imx_gpio_5, DT_GPIO_IMX_PORT_5_NAME,
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imx_gpio_5_init,
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&imx_gpio_5_data, &imx_gpio_5_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_5_init(struct device *dev)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_0,
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DT_GPIO_IMX_PORT_5_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0);
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irq_enable(DT_GPIO_IMX_PORT_5_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_5_IRQ_1,
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DT_GPIO_IMX_PORT_5_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_5), 0);
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irq_enable(DT_GPIO_IMX_PORT_5_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_5 */
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#ifdef CONFIG_GPIO_IMX_PORT_6
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static int imx_gpio_6_init(struct device *dev);
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static const struct imx_gpio_config imx_gpio_6_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_6_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_6_data;
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DEVICE_AND_API_INIT(imx_gpio_6, DT_GPIO_IMX_PORT_6_NAME,
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imx_gpio_6_init,
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&imx_gpio_6_data, &imx_gpio_6_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_6_init(struct device *dev)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_0,
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DT_GPIO_IMX_PORT_6_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0);
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irq_enable(DT_GPIO_IMX_PORT_6_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_6_IRQ_1,
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DT_GPIO_IMX_PORT_6_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_6), 0);
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irq_enable(DT_GPIO_IMX_PORT_6_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_6 */
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#ifdef CONFIG_GPIO_IMX_PORT_7
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static int imx_gpio_7_init(struct device *dev);
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static const struct imx_gpio_config imx_gpio_7_config = {
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.base = (GPIO_Type *)DT_GPIO_IMX_PORT_7_BASE_ADDRESS,
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};
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static struct imx_gpio_data imx_gpio_7_data;
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DEVICE_AND_API_INIT(imx_gpio_7, DT_GPIO_IMX_PORT_7_NAME,
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imx_gpio_7_init,
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&imx_gpio_7_data, &imx_gpio_7_config,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,
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&imx_gpio_driver_api);
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static int imx_gpio_7_init(struct device *dev)
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{
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IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_0,
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DT_GPIO_IMX_PORT_7_IRQ_0_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0);
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irq_enable(DT_GPIO_IMX_PORT_7_IRQ_0);
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IRQ_CONNECT(DT_GPIO_IMX_PORT_7_IRQ_1,
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DT_GPIO_IMX_PORT_7_IRQ_1_PRI,
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imx_gpio_port_isr, DEVICE_GET(imx_gpio_7), 0);
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irq_enable(DT_GPIO_IMX_PORT_7_IRQ_1);
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return 0;
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}
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#endif /* CONFIG_GPIO_IMX_PORT_7 */
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