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https://github.com/zephyrproject-rtos/zephyr
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995a9ba72a
Support for Freescale/NXP K64 SPI modules, limited to: - Master mode - A single active set of clock and transfer attributes (CTAR0), which includes non-adjustable delay parameters - Tx FIFO fill and Rx FIFO drain interrupt handling - Standard, continuous select and continuous SCK SPI transfer formats Also, divide-by-zero code generation in this driver is prevented. The 'volatile' attribute is added to some of the variables in the baud rate and delay calculation functions of the K64 SPI driver in order to prevent bad code generation by gcc toolchains for ARM seen when an optimization setting above -O0 is used. Specifically, a register is loaded with the constant 0 and is used as the divisor in a following divide instruction, resulting in a divide-by-zero exception. This issue has been seen with gcc versions 4.8.1 (the VxWorks toolchain) and 5.2.0 (the Zephyr SDK toolchain). Change-Id: Ib5b2b748aad8fdfd5e8d40544e6e1abef3713abe Signed-off-by: Jeff Blais <jeff.blais@windriver.com>
174 lines
5.3 KiB
C
174 lines
5.3 KiB
C
/* spi_k64_priv.h - Freescale K64 SPI driver private definitions */
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/*
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* Copyright (c) 2015-2016 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __SPI_K64_PRIV_H__
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#define __SPI_K64_PRIV_H__
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typedef void (*spi_k64_config_t)(void);
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struct spi_k64_config {
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uint32_t regs; /* base address of SPI module registers */
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uint32_t clk_gate_reg; /* SPI module's clock gate register addr. */
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uint32_t clk_gate_bit; /* SPI module's clock gate bit position */
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uint32_t irq; /* SPI module IRQ number */
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spi_k64_config_t config_func; /* IRQ configuration function pointer */
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};
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struct spi_k64_data {
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uint8_t frame_sz; /* frame/word size, in bits */
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uint8_t cont_pcs_sel; /* continuous slave/PCS selection enable */
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uint8_t pcs; /* slave/PCS selection */
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const uint8_t *tx_buf;
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uint32_t tx_buf_len;
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uint8_t *rx_buf;
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uint32_t rx_buf_len;
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uint32_t xfer_len;
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device_sync_call_t sync_info; /* sync call information */
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uint8_t error; /* error condition */
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};
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/* Data transfer signal timing delays */
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enum spi_k64_delay_id {
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DELAY_PCS_TO_SCK,
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DELAY_AFTER_SCK,
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DELAY_AFTER_XFER
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};
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/* Register offsets */
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#define SPI_K64_REG_MCR (0x00)
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#define SPI_K64_REG_TCR (0x08)
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#define SPI_K64_REG_CTAR0 (0x0C)
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#define SPI_K64_REG_CTAR1 (0x10)
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#define SPI_K64_REG_SR (0x2C)
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#define SPI_K64_REG_RSER (0x30)
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#define SPI_K64_REG_PUSHR (0x34)
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#define SPI_K64_REG_POPR (0x38)
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#define SPI_K64_REG_TXFR0 (0x3C)
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#define SPI_K64_REG_RXFR0 (0x7C)
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/* Module Control Register (MCR) settings */
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#define SPI_K64_MCR_HALT (0x1)
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#define SPI_K64_MCR_HALT_BIT (0)
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#define SPI_K64_MCR_SMPL_PT_MSK (0x3 << 8)
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#define SPI_K64_MCR_CLR_RXF (0x1 << 10)
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#define SPI_K64_MCR_CLR_TXF (0x1 << 11)
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#define SPI_K64_MCR_DIS_RXF (0x1 << 12)
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#define SPI_K64_MCR_DIS_TXF (0x1 << 13)
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#define SPI_K64_MCR_MDIS (0x1 << 14)
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#define SPI_K64_MCR_MDIS_BIT (14)
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#define SPI_K64_MCR_DOZE (0x1 << 15)
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#define SPI_K64_MCR_PCSIS_MSK (0x3F << 16)
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#define SPI_K64_MCR_PCSIS_SET(pcsis) ((pcsis) << 16)
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#define SPI_K64_MCR_ROOE (0x1 << 24)
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#define SPI_K64_MCR_PCSSE (0x1 << 25)
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#define SPI_K64_MCR_MTFE (0x1 << 26)
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#define SPI_K64_MCR_FRZ (0x1 << 27)
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#define SPI_K64_MCR_DCONF_MSK (0x3 << 28)
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#define SPI_K64_MCR_CONT_SCKE (0x1 << 30)
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#define SPI_K64_MCR_CONT_SCKE_SET(cont) ((cont) << 30)
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#define SPI_K64_MCR_MSTR (0x1 << 31)
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/* Clock and Transfer Attributes Register (CTAR) settings */
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#define SPI_K64_CTAR_BR_MSK (0xF)
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#define SPI_K64_CTAR_DT_MSK (0xF << 4)
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#define SPI_K64_CTAR_DT_SET(dt) ((dt) << 4)
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#define SPI_K64_CTAR_ASC_MSK (0xF << 8)
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#define SPI_K64_CTAR_ASC_SET(asc) ((asc) << 8)
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#define SPI_K64_CTAR_CSSCK_MSK (0xF << 12)
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#define SPI_K64_CTAR_CSSCK_SET(cssck) ((cssck) << 12)
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#define SPI_K64_CTAR_PBR_MSK (0x3 << 16)
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#define SPI_K64_CTAR_PBR_SET(pbr) ((pbr) << 16)
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#define SPI_K64_CTAR_PDT_MSK (0xF << 18)
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#define SPI_K64_CTAR_PDT_SET(pdt) ((pdt) << 18)
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#define SPI_K64_CTAR_PASC_MSK (0xF << 20)
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#define SPI_K64_CTAR_PASC_SET(pasc) ((pasc) << 20)
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#define SPI_K64_CTAR_PCSSCK_MSK (0xF << 22)
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#define SPI_K64_CTAR_PCSSCK_SET(pcssck) ((pcssck) << 22)
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#define SPI_K64_CTAR_LSBFE (0x1 << 24)
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#define SPI_K64_CTAR_CPHA (0x1 << 25)
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#define SPI_K64_CTAR_CPOL (0x1 << 26)
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#define SPI_K64_CTAR_FRMSZ_MSK (0xF << 27)
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#define SPI_K64_CTAR_FRMSZ_SET(sz) ((sz) << 27)
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#define SPI_K64_CTAR_DBR (0x1 << 31)
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#define SPI_K64_CTAR_DBR_SET(dbr) ((dbr) << 31)
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/* Status Register (SR) settings */
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#define SPI_K64_SR_POPNXTPTR_MSK (0xF)
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#define SPI_K64_SR_RXCTR_MSK (0xF << 4)
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#define SPI_K64_SR_TXNXTPTR_MSK (0xF << 8)
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#define SPI_K64_SR_TXCTR_MSK (0xF << 12)
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#define SPI_K64_SR_RFDF (0x1 << 17)
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#define SPI_K64_SR_RFOF (0x1 << 19)
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#define SPI_K64_SR_TFFF (0x1 << 25)
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#define SPI_K64_SR_TFUF (0x1 << 27)
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#define SPI_K64_SR_EOQF (0x1 << 28)
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#define SPI_K64_SR_TXRXS (0x1 << 30)
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#define SPI_K64_SR_TCF (0x1 << 31)
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/* DMA/Interrupt Request Select and Enable Register (RSER) settings */
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#define SPI_K64_RSER_RFDF_DIRS (0x1 << 16)
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#define SPI_K64_RSER_RFDF_RE (0x1 << 17)
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#define SPI_K64_RSER_RFOF_RE (0x1 << 19)
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#define SPI_K64_RSER_TFFF_DIRS (0x1 << 24)
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#define SPI_K64_RSER_TFFF_RE (0x1 << 25)
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#define SPI_K64_RSER_TFUF_RE (0x1 << 27)
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#define SPI_K64_RSER_EOQF_RE (0x1 << 28)
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#define SPI_K64_RSER_TCF_RE (0x1 << 31)
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/* Push Tx FIFO Register (PUSHR) settings */
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#define SPI_K64_PUSHR_TXDATA_MSK (0xFF)
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#define SPI_K64_PUSHR_PCS_MSK (0x3F << 16)
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#define SPI_K64_PUSHR_PCS_SET(pcs) ((pcs) << 16)
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#define SPI_K64_PUSHR_CTCNT (0x1 << 26)
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#define SPI_K64_PUSHR_EOQ (0x1 << 27)
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#define SPI_K64_PUSHR_CTAS_MSK (0x7 << 28)
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#define SPI_K64_PUSHR_CONT (0x1 << 31)
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#define SPI_K64_PUSHR_CONT_SET(cont) ((cont) << 31)
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/* Tx FIFO Register (TXFR) settings */
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#define SPI_K64_TXFR_TXDATA_MSK (0xFFFF)
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#define SPI_K64_TXFR_TXCMD_MSK (0xFFFF << 16)
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#endif /* __SPI_K64_PRIV_H__ */
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