Maureen Helm bc9f67f97f arch: soc: riscv32: Separate soc offsets from soc context save ... The zero-riscy core on the rv32m1 soc does not implement hardware loop extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes from GEN_SOC_OFFSET_SYMS(). Split out the soc offset symbols into a separate config so we can enable them without enabling soc context saving. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>		2019-05-06 14:52:17 -05:00
..
core	arch: soc: riscv32: Separate soc offsets from soc context save	2019-05-06 14:52:17 -05:00
include	arch: all: Remove not used struct _caller_saved	2019-04-18 12:24:56 -07:00
CMakeLists.txt	license: cleanup: add SPDX Apache-2.0 license identifier	2019-04-07 08:45:22 -04:00
Kconfig	arch: soc: riscv32: Separate soc offsets from soc context save	2019-05-06 14:52:17 -05:00