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https://github.com/zephyrproject-rtos/zephyr
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12a27f31a1
Those dtsi are a base for a range of 32-bit platforms. Setting this compatible makes it easier to distinguish all 32-bit x86 platforms. Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com> Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com> y
50 lines
932 B
Plaintext
50 lines
932 B
Plaintext
/*
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* Copyright (c) 2021 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,lakemont", "intel,x86";
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d-cache-line-size = <64>;
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reg = <0>;
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};
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};
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intc: ioapic@fec00000 {
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compatible = "intel,ioapic";
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reg = <0xfec00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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intc_loapic: loapic@fee00000 {
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compatible = "intel,loapic";
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reg = <0xfee00000 0x1000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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/*
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* Platforms with Lakemont SoC can have different hardware
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* configurations. So RAM and peripherals need to be
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* defined in the board configuration's DTS.
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*/
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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};
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};
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