mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-08 14:12:47 +00:00
d072ab83ac
This patch enables SPI4 on the 96Boards STM32 Sensors Mezzanine. SPI4 has been broken out to a Grove Connector on the board. Changes: - Updated board dts to enable spi4 - Updated board Kconfig - Updated board documentation - Update board pinmux - Updated stm32f4 pinmux header file - Updated stm32f401 dtsi - Updated stm32f4 defconfig to enable PORTE GPIO - Added board to spi_loopback test Test: spi_loopback test passed Signed-off-by: Sahaj Sarup <sahaj.sarup@linaro.org>
100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/*
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* Copyright (c) 2018 Linaro Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <drivers/pinmux.h>
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#include <sys/sys_io.h>
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#include <pinmux/stm32/pinmux_stm32.h>
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/* pin assignments for 96b_stm32_sensor_mez board */
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static const struct pin_config pinconf[] = {
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#ifdef CONFIG_UART_1
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{STM32_PIN_PA9, STM32F4_PINMUX_FUNC_PA9_USART1_TX},
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{STM32_PIN_PA10, STM32F4_PINMUX_FUNC_PA10_USART1_RX},
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#endif /* CONFIG_UART_1 */
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#ifdef CONFIG_UART_2
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{STM32_PIN_PD5, STM32F4_PINMUX_FUNC_PD5_USART2_TX},
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{STM32_PIN_PD6, STM32F4_PINMUX_FUNC_PD6_USART2_RX},
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#endif /* CONFIG_UART_2 */
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#ifdef CONFIG_UART_3
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{STM32_PIN_PD8, STM32F4_PINMUX_FUNC_PD8_USART3_TX},
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{STM32_PIN_PD9, STM32F4_PINMUX_FUNC_PD9_USART3_RX},
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#endif /* CONFIG_UART_3 */
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#ifdef CONFIG_UART_4
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{STM32_PIN_PC10, STM32F4_PINMUX_FUNC_PC10_UART4_TX},
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{STM32_PIN_PC11, STM32F4_PINMUX_FUNC_PC11_UART4_RX},
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#endif /* CONFIG_UART_4 */
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#ifdef CONFIG_I2C_1
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{STM32_PIN_PB6, STM32F4_PINMUX_FUNC_PB6_I2C1_SCL},
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{STM32_PIN_PB7, STM32F4_PINMUX_FUNC_PB7_I2C1_SDA},
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#endif /* CONFIG_I2C_1 */
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#ifdef CONFIG_I2C_2
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{STM32_PIN_PB10, STM32F4_PINMUX_FUNC_PB10_I2C2_SCL},
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{STM32_PIN_PC12, STM32F4_PINMUX_FUNC_PC12_I2C2_SDA},
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#endif /* CONFIG_I2C_2 */
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#ifdef CONFIG_SPI_1
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#ifdef CONFIG_SPI_STM32_USE_HW_SS
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{STM32_PIN_PA4, STM32F4_PINMUX_FUNC_PA4_SPI1_NSS |
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STM32_OSPEEDR_VERY_HIGH_SPEED},
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#endif /* CONFIG_SPI_STM32_USE_HW_SS */
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{STM32_PIN_PA5, STM32F4_PINMUX_FUNC_PA5_SPI1_SCK |
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STM32_OSPEEDR_VERY_HIGH_SPEED},
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{STM32_PIN_PA6, STM32F4_PINMUX_FUNC_PA6_SPI1_MISO},
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{STM32_PIN_PA7, STM32F4_PINMUX_FUNC_PA7_SPI1_MOSI},
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#endif /* CONFIG_SPI_1 */
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#ifdef CONFIG_SPI_2
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#ifdef CONFIG_SPI_STM32_USE_HW_SS
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{STM32_PIN_PB9, STM32F4_PINMUX_FUNC_PB9_SPI2_NSS |
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STM32_OSPEEDR_VERY_HIGH_SPEED},
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#endif /* CONFIG_SPI_STM32_USE_HW_SS */
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{STM32_PIN_PD3, STM32F4_PINMUX_FUNC_PD3_SPI2_SCK |
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STM32_OSPEEDR_VERY_HIGH_SPEED},
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{STM32_PIN_PB14, STM32F4_PINMUX_FUNC_PB14_SPI2_MISO},
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{STM32_PIN_PB15, STM32F4_PINMUX_FUNC_PB15_SPI2_MOSI},
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#endif /* CONFIG_SPI_2 */
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#ifdef CONFIG_SPI_4
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#ifdef CONFIG_SPI_STM32_USE_HW_SS
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{STM32_PIN_PE11, STM32F4_PINMUX_FUNC_PE11_SPI4_NSS |
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STM32_OSPEEDR_VERY_HIGH_SPEED},
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#endif /* CONFIG_SPI_STM32_USE_HW_SS */
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{STM32_PIN_PE12, STM32F4_PINMUX_FUNC_PE12_SPI4_SCK |
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STM32_OSPEEDR_VERY_HIGH_SPEED},
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{STM32_PIN_PE13, STM32F4_PINMUX_FUNC_PE13_SPI4_MISO},
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{STM32_PIN_PE14, STM32F4_PINMUX_FUNC_PE14_SPI4_MOSI},
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#endif /* CONFIG_SPI_4 */
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#ifdef CONFIG_I2S_2
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{STM32_PIN_PC7, STM32F4_PINMUX_FUNC_PC7_I2S2_CK},
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{STM32_PIN_PC1, STM32F4_PINMUX_FUNC_PC1_I2S2_SD},
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#endif /* CONFIG_I2S_2 */
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#ifdef CONFIG_PWM_STM32_3
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{ STM32_PIN_PB4, STM32F4_PINMUX_FUNC_PB4_PWM3_CH1 },
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{ STM32_PIN_PC8, STM32F4_PINMUX_FUNC_PC8_PWM3_CH3 },
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#endif /* CONFIG_PWM_STM32_3 */
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#ifdef CONFIG_PWM_STM32_4
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{ STM32_PIN_PD14, STM32F4_PINMUX_FUNC_PD14_PWM4_CH3 },
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{ STM32_PIN_PD15, STM32F4_PINMUX_FUNC_PD15_PWM4_CH4 },
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#endif /* CONFIG_PWM_STM32_4 */
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#ifdef CONFIG_PWM_STM32_9
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{ STM32_PIN_PE5, STM32F4_PINMUX_FUNC_PE5_PWM9_CH1 },
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{ STM32_PIN_PE6, STM32F4_PINMUX_FUNC_PE6_PWM9_CH2 },
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#endif /* CONFIG_PWM_STM32_9 */
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};
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static int pinmux_stm32_init(struct device *port)
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{
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ARG_UNUSED(port);
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stm32_setup_pins(pinconf, ARRAY_SIZE(pinconf));
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return 0;
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}
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SYS_INIT(pinmux_stm32_init, PRE_KERNEL_1,
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CONFIG_PINMUX_STM32_DEVICE_INITIALIZATION_PRIORITY);
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