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https://github.com/zephyrproject-rtos/zephyr
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38e17b68e3
The x86 paging code has been rewritten to support another paging mode and non-identity virtual mappings. - Paging code now uses an array of paging level characteristics and walks tables using for loops. This is opposed to having different functions for every paging level and lots of #ifdefs. The code is now more concise and adding new paging modes should be trivial. - We now support 32-bit, PAE, and IA-32e page tables. - The page tables created by gen_mmu.py are now installed at early boot. There are no longer separate "flat" page tables. These tables are mutable at any time. - The x86_mmu code now has a private header. Many definitions that did not need to be in public scope have been moved out of mmustructs.h and either placed in the C file or in the private header. - Improvements to dumping page table information, with the physical mapping and flags all shown - arch_mem_map() implemented - x86 userspace/memory domain code ported to use the new infrastructure. - add logic for physical -> virtual instruction pointer transition, including cleaning up identity mappings after this takes place. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com> |
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| arc | ||
| arm | ||
| common | ||
| nios2 | ||
| posix | ||
| riscv | ||
| x86 | ||
| xtensa | ||
| arch_inlines.h | ||
| cpu.h | ||
| syscall.h | ||