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For the EM Starterkit, one SOC I will soon be adding is EM7D. This SOC has FIRQ, but only has one register bank. Thus the interrupt handling for FIRQ needs to be different when CONFIG_RGF_NUM_BANKS==1. The handler must instead push registers onto the stack in the same stack frame layout that RIRQ uses. This allows for context switch to be easily done since its compatible. The common interrupt entry point _isr_enter must save r0 before using it, because in the FIRQ 1-bank case, it would be destroyed otherwise. So a global variable named saved_r0 has been added for this reason. The stack cannot be used to save r0, because it first has to determine whether its FIRQ or RIRQ here. This change has been tested on the EM Starterkit with EM7D SOC changes -- coming soon. To make the review easier, these 3 files are submitted first. Also, exceptions will no longer use the _firq_stack. This stack is not needed in the 1-bank case, but an exception stack is needed. I've added a new stack called _exception_stack, and made it be 512B, which should be enough for one exception. See ZEP-966 Change-Id: I6f228b840da7c4db440dd1cfef4ae25336c87f0d Signed-off-by: Chuck Jordan <cjordan@synopsys.com> |
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