Robert Winkler b18309c0d7 boards: doc: Add information about generating litex_vexriscv SoC ... This commit adds more information about the litex_vexrscv board target, including references to related projects and instruction about generating bitstream for the Digilent Arty A7-35T Board. Signed-off-by: Robert Winkler <rwinkler@antmicro.com>		2020-12-16 12:49:16 -05:00
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arc	board: arc: accommodate upstream OpenOCD for ARC	2020-12-16 14:27:23 +01:00
arm	boards: reel_board: remove non-minimal peripherals	2020-12-15 15:37:18 -06:00
common	ARC: west: split mdb runner for mdb-hw & mdb-nsim runners	2020-11-11 08:18:38 -05:00
nios2
posix	posix: Add cpu_hold() function to better emulate code delay	2020-12-14 12:32:11 +01:00
riscv	boards: doc: Add information about generating litex_vexriscv SoC	2020-12-16 12:49:16 -05:00
shields	shields: enable SD card support on Waveshare Epaper shield	2020-12-07 12:56:13 +01:00
sparc	boards: set CPU_HAS_FPU on LEON3 soc and boards	2020-12-04 14:33:43 +02:00
x86	Revert "boards/x86: Enable Intel VT-D for up_squared"	2020-12-14 23:21:41 -05:00
xtensa
CMakeLists.txt
deprecated.cmake
index.rst	boards: Add qemu_leon3	2020-11-13 14:53:55 -08:00
Kconfig	cmake: ensure shields can be placed in other BOARD_ROOTs	2020-11-13 13:36:48 +01:00