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3f5af00529
The patch adds a driver for STM32F10x series RCC (Reset and Clock Control) subsystem. The module is primarily responsible for setting up of MCU's clock tree. In particular the driver sets up SYSCLK, PLL (with source configuration), AHB prescaler, and APB1/APB2 prescalers. As part of this functionality, the subsystem can enable/disable clock signal for particular peripherals, thus reducing the power consumption of the MCU. The driver implements clock control driver API. However, subsystem IDs being HW specific are exposed in driver public header that must be included by callers. The driver registers a single device using a common name STM32_CLOCK_CONTROL_NAME. The device is initialized at the PRIMARY level with priority 1. This allows the initialization to take place right after SoC initialization routine. The driver depends on selection of SOC_STM32F1X config option and is MCU specific. Change-Id: I8bea5db20726a24bce7b7ffe0b95de543240429a Origin: Original Signed-off-by: Maciej Borzecki <maciek.borzecki@gmail.com>
113 lines
2.6 KiB
Plaintext
113 lines
2.6 KiB
Plaintext
# Kconfig - STM32F1 MCU clock control driver config
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#
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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if SOC_STM32F1X
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config CLOCK_CONTROL_STM32F10X
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bool
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prompt "STM32F10x Reset & Clock Control"
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depends on CLOCK_CONTROL && SOC_STM32F1X
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default y if SOC_STM32F1X
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help
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Enable driver for Reset & Clock Control subsystem found
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in STM32F1 family of MCUs
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config CLOCK_CONTROL_STM32F10X_DEVICE_PRIORITY
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int "Clock Control Device Priority"
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default 1
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depends on CLOCK_CONTROL_STM32F10X
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help
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This option controls the priority of clock control
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device initialization. Higher priority ensures that the device
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is initialized earlier in the startup cycle. If unsure, leave
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at default value 1
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choice
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prompt "STM32F10x System Clock Source"
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depends on CLOCK_CONTROL_STM32F10X
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config CLOCK_STM32F10X_SYSCLK_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of SYSCLK
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config CLOCK_STM32F10X_SYSCLK_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of SYSCLK
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config CLOCK_STM32F10X_SYSCLK_SRC_PLL
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bool "PLL"
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help
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Use PLL as source of SYSCLK
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endchoice
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choice
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prompt "STM32F10x PLL Clock Source"
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depends on CLOCK_CONTROL_STM32F10X
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config CLOCK_STM32F10X_PLL_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of PLL
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config CLOCK_STM32F10X_PLL_SRC_PREDIV1
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bool "PREDIV1"
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help
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Use PREDIV1 as source of PLL
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endchoice
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config CLOCK_STM32F10X_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_CONTROL_STM32F10X
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default 9
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range 2 16
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help
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PLL multiplier, allowed values: 2-16
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config CLOCK_STM32F10X_AHB_PRESCALER
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int "AHB prescaler"
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depends on CLOCK_CONTROL_STM32F10X
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default 0
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range 0 512
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help
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AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32F10X_APB1_PRESCALER
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int "APB1 prescaler"
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depends on CLOCK_CONTROL_STM32F10X
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default 0
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range 0 16
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help
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APB1 Low speed clock (PCLK1) prescaler, allowed values:
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0, 2, 4, 8, 16
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config CLOCK_STM32F10X_APB2_PRESCALER
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int "APB2 prescaler"
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depends on CLOCK_CONTROL_STM32F10X
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default 0
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range 0 16
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help
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APB2 High speed clock (PCLK2) prescaler, allowed values:
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0, 2, 4, 8, 16
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endif
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