Maureen Helm 948ef47cf4 dts: riscv32: Add rv32m1 zero-riscy core support ... Refactors peripheral addresses, clocks, and compatibles from the ri5cy core dtsi into a common soc dtsi, then attaches interrupts in core-specific dtsi files. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>		2019-05-06 14:52:17 -05:00
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arc
arm
bindings
common
nios2
riscv32	dts: riscv32: Add rv32m1 zero-riscy core support	2019-05-06 14:52:17 -05:00
x86	boards/x86/up_squared: move UART configuration to apollo_lake.dtsi	2019-05-04 18:29:32 -04:00
xtensa
Kconfig