mirror of
https://github.com/zephyrproject-rtos/zephyr
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b4edcb80cc
IRQ_CONNECT_STATIC now has the IRQ flags as the sixth parameter. Change-Id: Ib3efe15a128d74b84d83df3f8aeb39cdcea5ee41 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
157 lines
3.5 KiB
C
157 lines
3.5 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <nanokernel.h>
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#include <sys_io.h>
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#include <stdio.h>
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#include <rtc.h>
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#include <init.h>
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#include "board.h"
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#include "rtc_dw.h"
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#define CLK_RTC_DIV_DEF_MASK (0xFFFFFF83)
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#define CCU_RTC_CLK_DIV_EN (2)
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static void (*rtc_dw_cb_fn)(void);
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static void rtc_dw_set_div(const enum clk_rtc_div div)
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{
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/* set default division mask */
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uint32_t reg =
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sys_read32(CLOCK_SYSTEM_CLOCK_CONTROL) & CLK_RTC_DIV_DEF_MASK;
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reg |= (div << CCU_RTC_CLK_DIV_OFFSET);
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sys_write32(reg, CLOCK_SYSTEM_CLOCK_CONTROL);
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/* CLK Div en bit must be written from 0 -> 1 to apply new value */
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sys_set_bit(CLOCK_SYSTEM_CLOCK_CONTROL, CCU_RTC_CLK_DIV_EN);
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}
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/**
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* @brief Function to enable clock gating for the RTC
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* @return N/A
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*/
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static void rtc_dw_enable(void)
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{
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sys_set_bit(CLOCK_PERIPHERAL_BASE_ADDR, 11);
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sys_set_bit(CLOCK_PERIPHERAL_BASE_ADDR, 1);
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}
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/**
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* @brief Function to disable clock gating for the RTC
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* @return N/A
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*/
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static void rtc_dw_disable(void)
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{
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sys_clear_bit(CLOCK_PERIPHERAL_BASE_ADDR, 11);
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}
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/**
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* @brief RTC alarm ISR
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*
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* calls a user defined callback
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*
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* @return N/A
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*/
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void rtc_dw_isr(void)
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{
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/* Disable RTC interrupt */
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sys_clear_bit(RTC_BASE_ADDR + RTC_CCR, 0);
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if (rtc_dw_cb_fn) {
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(*rtc_dw_cb_fn)();
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}
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/* clear interrupt */
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sys_read32(RTC_BASE_ADDR + RTC_EOI);
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}
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IRQ_CONNECT_STATIC(rtc, INT_RTC_IRQ, CONFIG_RTC_IRQ_PRI, rtc_dw_isr, 0, 0);
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/**
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* @brief Sets an RTC alarm
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* @param alarm_val Alarm value
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* @return 0 on success
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*/
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static int rtc_dw_set_alarm(const uint32_t alarm_val)
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{
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sys_set_bit(RTC_BASE_ADDR + RTC_CCR, 0);
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sys_write32(alarm_val, RTC_BASE_ADDR + RTC_CMR);
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return DEV_OK;
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}
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/**
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* @brief Function to configure the RTC
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* @param config pointer to a RTC configuration structure
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* @return 0 on success
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*/
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static int rtc_dw_set_config(struct rtc_config *config)
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{
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/* Set RTC divider - 32768 / 32.768 khz = 1 second. */
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rtc_dw_set_div(RTC_DIVIDER);
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/* set initial RTC value */
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sys_write32(config->init_val, RTC_BASE_ADDR + RTC_CLR);
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/* clear any pending interrupts */
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sys_read32(RTC_BASE_ADDR + RTC_EOI);
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rtc_dw_cb_fn = config->cb_fn;
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if (config->alarm_enable) {
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rtc_dw_set_alarm(config->alarm_val);
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} else {
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sys_clear_bit(RTC_BASE_ADDR + RTC_CCR, 0);
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}
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return DEV_OK;
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}
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/**
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* @brief Read current RTC value
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* @return current rtc value
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*/
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static uint32_t rtc_dw_read(void)
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{
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return sys_read32(RTC_BASE_ADDR + RTC_CCVR);
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}
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static struct rtc_driver_api funcs = {
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.set_config = rtc_dw_set_config,
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.read = rtc_dw_read,
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.enable = rtc_dw_enable,
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.disable = rtc_dw_disable,
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.set_alarm = rtc_dw_set_alarm,
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};
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int rtc_dw_init(struct device *dev)
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{
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IRQ_CONFIG(rtc, INT_RTC_IRQ, 0);
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irq_enable(INT_RTC_IRQ);
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SCSS_INTERRUPT->int_rtc_mask = INT_UNMASK_IA;
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dev->driver_api = &funcs;
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return DEV_OK;
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}
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struct rtc_dw_dev_config rtc_dev = {
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.base_address = RTC_BASE_ADDR,
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};
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#ifdef CONFIG_RTC_DW
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DECLARE_DEVICE_INIT_CONFIG(rtc, RTC_DRV_NAME, &rtc_dw_init, &rtc_dev);
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nano_early_init(rtc, NULL);
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#endif
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