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https://github.com/zephyrproject-rtos/zephyr
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176d184fb8
When going into DEEP_SLEEP mode, the ARC core now saves its context. This includes: - All core registers - Stack pointer - Program counter (restored by jumping to the restore code) The arc reset code now checks if the GPS0 bit 2 is set. This is similar to the behavior of the x86 core done by the QMSI bootloader which is setting GPS0 bit 1 in order to call the restore path instead of cold boot path. The sample has been adapted in order to support the ARC. Jira: ZEP-1222 Change-Id: I375f03b16b8a5fd1f07ead55cf7e4947d6290c9f Signed-off-by: Julien Delayen <julien.delayen@intel.com>
134 lines
2.9 KiB
ArmAsm
134 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2014 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Reset handler
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*
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* Reset handler that prepares the system for running C code.
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*/
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#define _ASMLANGUAGE
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// #include <board.h>
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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GDATA(_interrupt_stack)
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GDATA(_firq_stack)
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GDATA(_main_stack)
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/* use one of the available interrupt stacks during init */
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/* FIRQ only ? */
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#if CONFIG_NUM_IRQ_PRIO_LEVELS == 1
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/* FIRQ, but uses _interrupt_stack ? */
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#if CONFIG_RGF_NUM_BANKS == 1
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#define INIT_STACK _interrupt_stack
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#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
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#else
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#define INIT_STACK _firq_stack
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#define INIT_STACK_SIZE CONFIG_FIRQ_STACK_SIZE
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#endif
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#else
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#define INIT_STACK _interrupt_stack
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#define INIT_STACK_SIZE CONFIG_ISR_STACK_SIZE
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#endif
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GTEXT(__reset)
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GTEXT(__start)
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/**
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*
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* @brief Reset vector
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*
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* Ran when the system comes out of reset. The processor is at supervisor level.
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*
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* Locking interrupts prevents anything from interrupting the CPU.
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*
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* When these steps are completed, jump to _PrepC(), which will finish setting
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* up the system for running C code.
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*
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* @return N/A
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*/
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SECTION_FUNC(TEXT,__reset)
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SECTION_FUNC(TEXT,__start)
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/* lock interrupts: will get unlocked when switch to main task */
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clri
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mov r1, 1
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invalidate_and_disable_icache:
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lr r0, [_ARC_V2_I_CACHE_BUILD]
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and.f r0, r0, 0xff
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bz.nd invalidate_dcache
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mov_s r2, 0
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sr r2, [_ARC_V2_IC_IVIC]
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/* writing to IC_IVIC needs 3 NOPs */
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nop
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nop
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nop
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sr r1, [_ARC_V2_IC_CTRL]
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invalidate_dcache:
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lr r3, [_ARC_V2_D_CACHE_BUILD]
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and.f r3, r3, 0xff
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bz.nd done_cache_invalidate
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sr r1, [_ARC_V2_DC_IVDC]
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done_cache_invalidate:
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#if defined(CONFIG_SYS_POWER_DEEP_SLEEP) && \
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!defined(CONFIG_BOOTLOADER_CONTEXT_RESTORE)
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jl @_sys_soc_resume_from_deep_sleep
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#endif
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#ifdef CONFIG_INIT_STACKS
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/*
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* use the main stack to call memset on the interrupt stack and the
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* FIRQ stack when CONFIG_INIT_STACKS is enabled before switching to
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* one of them for the rest of the early boot
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*/
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mov sp, _main_stack
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add sp, sp, CONFIG_MAIN_STACK_SIZE
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mov_s r0, _interrupt_stack
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mov_s r1, 0xaa
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mov_s r2, CONFIG_ISR_STACK_SIZE
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jl memset
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#if CONFIG_RGF_NUM_BANKS != 1
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mov_s r0, _firq_stack
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mov_s r1, 0xaa
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mov_s r2, CONFIG_FIRQ_STACK_SIZE
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jl memset
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#endif
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#endif /* CONFIG_INIT_STACKS */
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mov sp, INIT_STACK
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add sp, sp, INIT_STACK_SIZE
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j @_PrepC
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