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zephyr/dts/riscv
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Yong Cong Sin 93cbfcfee9 board: riscv: qemu: increase ndev of PLIC to 1024 
Increase the `ndev` of PLIC to the max of 1024 from 53, as
supported by the RISCV PLIC. The total number of IRQs is now
1035(1024 + 11), up from 64(53 + 11).

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-10-05 06:10:06 -04:00
..
andes drivers: intc: plic: define all registers' offset in the driver 2023-10-04 09:06:28 -04:00
efinix drivers: intc: plic: define all registers' offset in the driver 2023-10-04 09:06:28 -04:00
espressif/esp32c3
gigadevice
ite
lowrisc drivers: intc: plic: define all registers' offset in the driver 2023-10-04 09:06:28 -04:00
microchip drivers: intc: plic: define all registers' offset in the driver 2023-10-04 09:06:28 -04:00
niosv
openisa
sifive drivers: intc: plic: define all registers' offset in the driver 2023-10-04 09:06:28 -04:00
starfive drivers: intc: plic: define all registers' offset in the driver 2023-10-04 09:06:28 -04:00
telink drivers: intc: plic: define all registers' offset in the driver 2023-10-04 09:06:28 -04:00
neorv32.dtsi
riscv32-litex-vexriscv.dtsi
virt.dtsi board: riscv: qemu: increase ndev of PLIC to 1024 2023-10-05 06:10:06 -04:00