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e51b24b429
The PLL Q divisor does not exist on stm32g0X0 variants. It should only be configured for g0X1 variants. Signed-off-by: Eric Hay <EHay@sierrawireless.com>
51 lines
1.1 KiB
Plaintext
51 lines
1.1 KiB
Plaintext
# STM32G0 PLL configuration options
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# Copyright (c) 2019 Linaro
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_STM32G0X
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config CLOCK_STM32_PLL_N_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 8
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range 8 86
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help
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PLL multiplier, allowed values: 8-86
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PLL output must not exceed 56MHz(1.8V)/26MHz(1.2V).
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config CLOCK_STM32_PLL_M_DIVISOR
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int "PLL divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 1
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range 1 8
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help
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PLL divisor, allowed values: 1-8.
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config CLOCK_STM32_PLL_P_DIVISOR
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int "PLL P Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 2 32
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help
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PLL P VCO divisor, allowed values: 2-32.
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config CLOCK_STM32_PLL_Q_DIVISOR
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int "PLL Q Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL && (SOC_STM32G031XX || SOC_STM32G071XX)
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default 2
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range 2 8
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help
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PLL Q VCO divisor, allowed values: 2-8.
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Limited to STM32G0X1 variants.
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config CLOCK_STM32_PLL_R_DIVISOR
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int "PLL R Divisor"
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depends on CLOCK_STM32_SYSCLK_SRC_PLL
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default 2
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range 2 8
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help
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PLL R VCO divisor, allowed values: 2-8.
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endif # SOC_SERIES_STM32G0X
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