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https://github.com/zephyrproject-rtos/zephyr
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b837252269
System clock for m4 core was set to same clock as m7 core. This is wrong as m4 its value is actually based on clock frequency value after D1CPRE (sys_d1cpre_ck) divided per HPRE value, 200MHz in current case. This also matches the max clock speed for the m4 core (200MHz) Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org> |
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| .. | ||
| arc | ||
| arm | ||
| common | ||
| nios2 | ||
| posix | ||
| riscv | ||
| shields | ||
| x86 | ||
| x86_64/qemu_x86_64 | ||
| xtensa | ||
| CMakeLists.txt | ||
| index.rst | ||
| Kconfig | ||