Ulf Magnusson 5d0db517b9 dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values ... Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0 binding. The new binding adds a required riscv,ndev property, which gives the number of external interrupts supported. Use the new binding for microsemi-miv.dtsi (with a value of 31 for riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf) and riscv32-fe310.dtsi (which already assigns riscv,ndev). Also remove a spurious riscv,ndev assignment from riscv32-litex-vexriscv.dtsi. Also make edtlib and the old scripts/dts/ scripts replace '.' in compatible strings with '_' when generating identifiers. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>		2019-08-02 11:44:09 +02:00
..
__init__.py
clocks.py	scripts/dts: Add deprecation comments to old scripts	2019-07-29 16:22:17 -04:00
compatible.py	dts: Make instance defines consistent	2019-07-30 17:10:31 -05:00
default.py	scripts/dts: Add deprecation comments to old scripts	2019-07-29 16:22:17 -04:00
directive.py	scripts/dts: Add deprecation comments to old scripts	2019-07-29 16:22:17 -04:00
flash.py	scripts/dts: Add deprecation comments to old scripts	2019-07-29 16:22:17 -04:00
globals.py	dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values	2019-08-02 11:44:09 +02:00
interrupts.py	scripts/dts: Add deprecation comments to old scripts	2019-07-29 16:22:17 -04:00
reg.py	scripts/dts: Add deprecation comments to old scripts	2019-07-29 16:22:17 -04:00