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fbd9dd4526
This adds support for the single-vector trapping (SVT) model, defined by SPARC-V8 Embedded (V8E) Architecture Specification. SVT is available in most LEON processors. With single-vector trapping enabled, all traps are vectored through a single trap vector (TBR.A) rather than one 16-byte entry for each trap type. This improves memory utilization because the full 4 KiB trap table is not needed. This implementation uses a two-level of lookup table to find the handler for the trap type (0..255). - Execution time is constant. - Condition flags are preserved. - The implementation footprint is 60 bytes .text and 284 bytes .rodata. For comparison, a non-SVT table is always 4096 .text. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
68 lines
1.2 KiB
Plaintext
68 lines
1.2 KiB
Plaintext
# Copyright (c) 2019-2020 Cobham Gaisler AB
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# SPDX-License-Identifier: Apache-2.0
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menu "SPARC Options"
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depends on SPARC
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config ARCH
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default "sparc"
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config SPARC_NWIN
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int "Number of register windows"
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default 8
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help
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Number of implemented register windows.
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config GEN_ISR_TABLES
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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config GEN_SW_ISR_TABLE
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default y
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config NUM_IRQS
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int
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default 32
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config SPARC_SVT
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bool "Single-vector trapping"
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help
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Use Single-vector trapping (SVT). Defined by SPARC-V8 Embedded (V8E)
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Architecture Specification and available in some LEON processors.
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config SPARC_CASA
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bool "CASA instructions"
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help
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Use CASA atomic instructions. Defined by SPARC V9 and available
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in some LEON processors.
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# The SPARC V8 ABI allocates a stack frame of minimum 96 byte for each SAVE
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# instruction so we bump the kernel default values.
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config MAIN_STACK_SIZE
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default 4096 if COVERAGE_GCOV
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default 2048
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config IDLE_STACK_SIZE
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default 1024
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config ISR_STACK_SIZE
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default 4096
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config TEST_EXTRA_STACK_SIZE
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default 4096 if COVERAGE_GCOV
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default 2048
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config IPM_CONSOLE_STACK_SIZE
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default 4096 if COVERAGE_GCOV
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default 1024
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config NET_TX_STACK_SIZE
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default 2048
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config NET_RX_STACK_SIZE
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default 2048
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endmenu
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