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https://github.com/zephyrproject-rtos/zephyr
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ea7922195b
The Atmel SAM0 SoC enable peripherals clocks in distinct places: PM and MCLK. The old devices had defined the peripheral clock enable bit at PM. On the newer devices this was extracted on a dedicated memory section called Master Clock (MCLK). This change excludes the dedicated bindings in favor of a generic approach that cover all cases. Now the clocks properties is complemented by the atmel,assigned-clocks property. It gives the liberty to user to customize the clock source from a generic clock or configure the direct connections. All peripherals drivers were reworked with the newer solution. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
169 lines
4.3 KiB
C
169 lines
4.3 KiB
C
/*
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* Copyright (c) 2020 Google LLC.
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* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* PWM driver using the SAM0 Timer/Counter (TCC) in Normal PWM (NPWM) mode.
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* Supports the SAMD21 and SAMD5x series.
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*/
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#define DT_DRV_COMPAT atmel_sam0_tcc_pwm
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#include <zephyr/device.h>
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#include <errno.h>
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#include <zephyr/drivers/pwm.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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/* clang-format off */
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/* Static configuration */
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struct pwm_sam0_config {
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Tcc *regs;
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const struct pinctrl_dev_config *pcfg;
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uint8_t channels;
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uint8_t counter_size;
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uint16_t prescaler;
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uint32_t freq;
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volatile uint32_t *mclk;
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uint32_t mclk_mask;
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uint32_t gclk_gen;
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uint16_t gclk_id;
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};
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/* Wait for the peripheral to finish all commands */
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static void wait_synchronization(Tcc *regs)
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{
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while (regs->SYNCBUSY.reg != 0) {
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}
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}
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static int pwm_sam0_get_cycles_per_sec(const struct device *dev,
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uint32_t channel, uint64_t *cycles)
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{
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const struct pwm_sam0_config *const cfg = dev->config;
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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*cycles = cfg->freq;
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return 0;
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}
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static int pwm_sam0_set_cycles(const struct device *dev, uint32_t channel,
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uint32_t period_cycles, uint32_t pulse_cycles,
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pwm_flags_t flags)
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{
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const struct pwm_sam0_config *const cfg = dev->config;
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Tcc *regs = cfg->regs;
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uint32_t top = 1 << cfg->counter_size;
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uint32_t invert_mask = 1 << channel;
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bool invert = ((flags & PWM_POLARITY_INVERTED) != 0);
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bool inverted = ((regs->DRVCTRL.vec.INVEN & invert_mask) != 0);
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if (channel >= cfg->channels) {
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return -EINVAL;
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}
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if (period_cycles >= top || pulse_cycles >= top) {
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return -EINVAL;
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}
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/*
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* Update the buffered width and period. These will be automatically
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* loaded on the next cycle.
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*/
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#ifdef TCC_PERBUF_PERBUF
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/* SAME51 naming */
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regs->CCBUF[channel].reg = TCC_CCBUF_CCBUF(pulse_cycles);
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regs->PERBUF.reg = TCC_PERBUF_PERBUF(period_cycles);
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#else
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/* SAMD21 naming */
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regs->CCB[channel].reg = TCC_CCB_CCB(pulse_cycles);
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regs->PERB.reg = TCC_PERB_PERB(period_cycles);
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#endif
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if (invert != inverted) {
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regs->CTRLA.bit.ENABLE = 0;
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wait_synchronization(regs);
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regs->DRVCTRL.vec.INVEN ^= invert_mask;
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regs->CTRLA.bit.ENABLE = 1;
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wait_synchronization(regs);
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}
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return 0;
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}
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static int pwm_sam0_init(const struct device *dev)
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{
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const struct pwm_sam0_config *const cfg = dev->config;
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Tcc *regs = cfg->regs;
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int retval;
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*cfg->mclk |= cfg->mclk_mask;
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#ifdef MCLK
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GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
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| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
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#else
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GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
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| GCLK_CLKCTRL_GEN(cfg->gclk_gen)
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| GCLK_CLKCTRL_ID(cfg->gclk_id);
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#endif
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retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (retval < 0) {
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return retval;
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}
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regs->CTRLA.bit.SWRST = 1;
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wait_synchronization(regs);
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regs->CTRLA.reg = cfg->prescaler;
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regs->WAVE.reg = TCC_WAVE_WAVEGEN_NPWM;
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regs->PER.reg = TCC_PER_PER(1);
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regs->CTRLA.bit.ENABLE = 1;
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wait_synchronization(regs);
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return 0;
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}
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static DEVICE_API(pwm, pwm_sam0_driver_api) = {
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.set_cycles = pwm_sam0_set_cycles,
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.get_cycles_per_sec = pwm_sam0_get_cycles_per_sec,
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};
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#define ASSIGNED_CLOCKS_CELL_BY_NAME \
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ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
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#define PWM_SAM0_INIT(inst) \
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PINCTRL_DT_INST_DEFINE(inst); \
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static const struct pwm_sam0_config pwm_sam0_config_##inst = { \
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.regs = (Tcc *)DT_INST_REG_ADDR(inst), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
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.channels = DT_INST_PROP(inst, channels), \
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.counter_size = DT_INST_PROP(inst, counter_size), \
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.prescaler = UTIL_CAT(TCC_CTRLA_PRESCALER_DIV, \
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DT_INST_PROP(inst, prescaler)), \
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.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / \
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DT_INST_PROP(inst, prescaler), \
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.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(inst, gclk, gen), \
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.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id), \
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.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(inst), \
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.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(inst, bit), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, &pwm_sam0_init, NULL, \
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NULL, &pwm_sam0_config_##inst, \
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POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, \
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&pwm_sam0_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PWM_SAM0_INIT)
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/* clang-format on */
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