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be217e4a3a
In npcx7 series, all of them support the Intel Enhanced Serial Peripheral Interface (eSPI) Revision 1.0. This specification provides a path for migrating host sub-devices via LPC to a lower pin count, higher bandwidth bus. In addition to Host communication via the peripheral channel, it provides virtual wires support, out-of-band communication, and device mastering option over the Chipset SPI flash. Becisdes introducing eSPI device in npcx7, this CL also includes: 1. Add eSPI device tree declarations. 2. Add npcx7-espi-vws-map.dtsi to present the relationship between eSPI Virtual-Wire signals, eSPI registers, and wake-up input sources. 3. Zephyr eSPI api implementation. 4, Add OOB (Out of Band tunneled SMBus) support. 5. Add configuration files for eSPI test suites. Signed-off-by: Mulin Chao <MLChao@nuvoton.com> |
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| atmel | ||
| broadcom | ||
| cypress | ||
| infineon | ||
| microchip | ||
| nordic | ||
| nuvoton | ||
| nxp | ||
| qemu-virt | ||
| quicklogic | ||
| silabs | ||
| st | ||
| ti | ||
| xilinx | ||
| armv6-m.dtsi | ||
| armv7-m.dtsi | ||
| armv7-r.dtsi | ||
| armv8-a.dtsi | ||
| armv8-m.dtsi | ||