Stephanos Ioannidis bea3ee0ed0 arch: arm: Fix incorrect Cortex-R interrupt state control logic. ... This commit fixes incorrect Cortex-R interrupt lock, unlock and state check function implementations. The issues can be summarised as follows: 1. The current implementation of 'z_arch_irq_lock' returns the value of CPSR as the IRQ key and, since CPSR contains many other state bits, this caused 'z_arch_irq_unlocked' to return false even when IRQ is unlocked. This problem is fixed by isolating only the I-bit of CPSR and returning this value as the IRQ key, such that it returns a non-zero value when interrupt is disabled. 2. The current implementation of 'z_arch_irq_unlock' directly updates the value of CPSR control field with the IRQ key and this can cause other state bits in CPSR to be corrupted. This problem is fixed by conditionally enabling interrupt using CPSIE instruction when the value of IRQ key is a zero. 3. The current implementation of 'z_arch_is_in_isr' checks the value of CPSR MODE field and returns true if its value is IRQ or FIQ. While this does not normally cause an issue, the function can return false when IRQ offloading is used because the offload function executes in SVC mode. This problem is fixed by adding check for SVC mode. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>		2020-02-11 08:03:37 -08:00
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arc	extensions.cmake: Replace TEXT_START with ROM_START	2020-01-23 03:22:59 -08:00
arm	arch: arm: Fix incorrect Cortex-R interrupt state control logic.	2020-02-11 08:03:37 -08:00
common
nios2	extensions.cmake: Replace TEXT_START with ROM_START	2020-01-23 03:22:59 -08:00
posix	dts: Rename generated_dts_board*.{h,conf} to devicetree*.{h,conf}	2020-01-17 17:57:59 +01:00
riscv	extensions.cmake: Replace TEXT_START with ROM_START	2020-01-23 03:22:59 -08:00
x86	x86: organize 64-bit ESF	2020-02-08 08:51:43 -05:00
xtensa	arch: xtensa: Add support for Intel Apollolake	2020-02-05 10:43:25 -05:00
arch_inlines.h
cpu.h	arch: arm64: Introduce ARM64 (AArch64) architecture	2020-02-01 08:08:43 -05:00
syscall.h