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Originally, x86 just supported APIC. Then later support for the Mint Valley Interrupt Controller was added. This controller is mostly similar to the APIC with some differences, but was integrated in a somewhat hacked-up fashion. Now we define irq_controller.h, which is a layer of abstraction between the core arch code and the interrupt controller implementation. Contents of the API: - Controllers with a fixed irq-to-vector mapping define _IRQ_CONTROLLER_VECTOR_MAPPING(irq) to obtain a compile-time map between the two. - _irq_controller_program() notifies the interrupt controller what vector will be used for a particular IRQ along with triggering flags - _irq_controller_isr_vector_get() reports the vector number of the IRQ currently being serviced - In assembly language domain, _irq_controller_eoi implements EOI handling. - Since triggering options can vary, some common defines for triggering IRQ_TRIGGER_EDGE, IRQ_TRIGGER_LEVEL, IRQ_POLARITY_HIGH, IRQ_POLARITY_LOW introduced. Specific changes made: - New Kconfig X86_FIXED_IRQ_MAPPING for those interrupt controllers that have a fixed relationship between IRQ lines and IDT vectors. - MVIC driver rewritten per the HAS instead of the tortuous methods used to get it to behave like LOAPIC. We are no longer writing values to reserved registers. Additional assertions added. - Some cleanup in the loapic_timer driver to make the MVIC differences clearer. - Unused APIs removed, or folded into calling code when used just once. - MVIC doesn't bother to write a -1 to the intList priority field since it gets ignored anyway Issue: ZEP-48 Change-Id: I071a477ea68c36e00c3d0653ce74b3583454154d Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
80 lines
2.5 KiB
C
80 lines
2.5 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MVIC_H
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#define MVIC_H
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#include <arch/cpu.h>
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/* Register defines. A lot of similarities to APIC, but not quite the same */
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#define MVIC_TPR 0xFEE00080 /* Task priority register */
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#define MVIC_PPR 0xFEE000A0 /* Process priority register */
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#define MVIC_EOI 0xFEE000B0 /* End-of-interrupt register */
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#define MVIC_SIVR 0xFEE000F0 /* Spurious interrupt vector register */
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#define MVIC_ISR 0xFEE00110 /* In-service register */
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#define MVIC_IRR 0xFEE00210 /* Interrupt request register */
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#define MVIC_LVTTIMER 0xFEE00320 /* Local vector table timer register */
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#define MVIC_ICR 0xFEE00380 /* Timer initial count register */
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#define MVIC_CCR 0xFEE00390 /* Timer current count register */
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#define MVIC_IOREGSEL 0xFEC00000 /* Register select (index) */
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#define MVIC_IOWIN 0xFEC00010 /* Register windows (data) */
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/* MVIC_LVTTIMER bits */
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#define MVIC_LVTTIMER_MASK BIT(16)
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#define MVIC_LVTTIMER_PERIODIC BIT(17)
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/* MVIC_IOWIN bits */
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#define MVIC_IOWIN_TRIGGER_LEVEL BIT(15)
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#define MVIC_IOWIN_TRIGGER_EDGE 0
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#define MVIC_IOWIN_MASK BIT(16)
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#define MVIC_IOWIN_SUPPORTED_BITS_MASK (MVIC_IOWIN_MASK | \
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MVIC_IOWIN_TRIGGER_LEVEL)
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/* MVIC IOREGSEL register usage defines */
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#define MVIC_LOW_NIBBLE_MASK 0x07
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#define MVIC_HIGH_NIBBLE_MASK 0x18
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#define MVIC_NUM_RTES 32
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#define _IRQ_TRIGGER_EDGE MVIC_IOWIN_TRIGGER_EDGE
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#define _IRQ_TRIGGER_LEVEL MVIC_IOWIN_TRIGGER_LEVEL
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/* MVIC does not support IRQ_POLARITY_HIGH or IRQ_POLARITY_LOW,
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* leave undefined
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*/
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#ifndef _ASMLANGUAGE
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/* Implementation of irq_controller.h interface */
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#define __IRQ_CONTROLLER_VECTOR_MAPPING(irq) ((irq) + 32)
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void __irq_controller_irq_config(unsigned int vector, unsigned int irq,
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uint32_t flags);
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int __irq_controller_isr_vector_get(void);
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#else /* _ASMLANGUAGE */
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.macro __irq_controller_eoi
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xorl %eax, %eax /* zeroes eax */
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movl %eax, MVIC_EOI /* tell MVIC the IRQ is handled */
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.endm
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#endif
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#endif /* MVIC_H */
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