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https://github.com/zephyrproject-rtos/zephyr
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caf50a52ea
It's possible that there's a queued event from the nRF51 at the point where we start resetting it, resulting in the stack receiving two NOP events. To prevent this, make sure to drain the UART while the controller is in a powered off state. Change-Id: Ic009e11c11ac750fc76c881c0ffe9bd12d38da0a Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/* nrf51-pm.c Power Management for nrf51 chip */
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/*
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* Copyright (c) 2016 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <gpio.h>
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#include <uart.h>
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#include <bluetooth/log.h>
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#include <errno.h>
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#define NBLE_SWDIO_PIN 6
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#define NBLE_RESET_PIN NBLE_SWDIO_PIN
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#define NBLE_BTWAKE_PIN 5
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static struct device *nrf51_gpio;
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int nrf51_enable(void)
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{
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return gpio_pin_write(nrf51_gpio, NBLE_BTWAKE_PIN, 1);
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}
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int nrf51_disable(void)
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{
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return gpio_pin_write(nrf51_gpio, NBLE_BTWAKE_PIN, 0);
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}
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static inline void sleep_ms(unsigned int ms)
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{
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switch (sys_execution_context_type_get()) {
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case NANO_CTX_FIBER:
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fiber_sleep(MSEC(ms));
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return;
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case NANO_CTX_TASK:
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task_sleep(MSEC(ms));
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return;
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default:
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BT_ERR("ISR context is not supported");
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return;
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}
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}
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int nrf51_init(struct device *dev)
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{
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uint8_t c;
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int ret;
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nrf51_gpio = device_get_binding("GPIO_0");
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if (!nrf51_gpio) {
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BT_ERR("Cannot find GPIO_0");
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return -ENODEV;
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}
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ret = gpio_pin_configure(nrf51_gpio, NBLE_RESET_PIN, GPIO_DIR_OUT);
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if (ret) {
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BT_ERR("Error configuring pin %d", NBLE_RESET_PIN);
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return -ENODEV;
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}
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/* Reset hold time is 0.2us (normal) or 100us (SWD debug) */
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ret = gpio_pin_write(nrf51_gpio, NBLE_RESET_PIN, 0);
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if (ret) {
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BT_ERR("Error pin write %d", NBLE_RESET_PIN);
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return -EINVAL;
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}
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/* Drain the fifo */
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while (uart_fifo_read(dev, &c, 1)) {
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continue;
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}
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/**
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* NBLE reset is achieved by asserting low the SWDIO pin.
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* However, the BLE Core chip can be in SWD debug mode,
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* and NRF_POWER->RESET = 0 due to, other constraints: therefore,
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* this reset might not work everytime, especially after
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* flashing or debugging.
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*/
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/* sleep 1ms depending on context */
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sleep_ms(1);
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ret = gpio_pin_write(nrf51_gpio, NBLE_RESET_PIN, 1);
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if (ret) {
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BT_ERR("Error pin write %d", NBLE_RESET_PIN);
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return -EINVAL;
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}
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/* Set back GPIO to input to avoid interfering with external debugger */
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ret = gpio_pin_configure(nrf51_gpio, NBLE_RESET_PIN, GPIO_DIR_IN);
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if (ret) {
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BT_ERR("Error configuring pin %d", NBLE_RESET_PIN);
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return -ENODEV;
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}
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ret = gpio_pin_configure(nrf51_gpio, NBLE_BTWAKE_PIN, GPIO_DIR_OUT);
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if (ret) {
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BT_ERR("Error configuring pin %d", NBLE_BTWAKE_PIN);
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return -ENODEV;
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}
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return nrf51_enable();
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}
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