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zephyr/dts/riscv32
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Filip Kokosinski 342cbc9e01 soc: riscv32: add LiteX VexRiscV SoC 
Add LiteX with softcore CPU VexRiscV SoC definitions and default
configurations.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2019-05-15 12:52:16 -05:00
..
microsemi-miv.dtsi dts: riscv32: microsemi-miv: add flash and sram 2019-05-10 10:34:31 -05:00
riscv32-fe310.dtsi soc/riscv32-fe310: add label for uart1 2019-04-25 09:19:14 -07:00
riscv32-litex-vexriscv.dtsi soc: riscv32: add LiteX VexRiscV SoC 2019-05-15 12:52:16 -05:00
rv32m1_ri5cy.dtsi soc: riscv32: Move rv32m1 flash memory definitions to dts 2019-05-06 19:09:59 -04:00
rv32m1_zero_riscy.dtsi soc: riscv32: Move rv32m1 flash memory definitions to dts 2019-05-06 19:09:59 -04:00
rv32m1.dtsi dts: riscv32: rv32m1: fix reg value for cpu@1 2019-05-07 08:39:27 -04:00