mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-06 12:21:56 +00:00
ac74d8b652
Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
136 lines
3.8 KiB
C
136 lines
3.8 KiB
C
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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/* STATUS register */
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#define ALTERA_AVALON_TIMER_STATUS_REG 0
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#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1)
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#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0)
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#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2)
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#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1)
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/* CONTROL register */
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#define ALTERA_AVALON_TIMER_CONTROL_REG 1
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#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1)
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#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0)
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#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2)
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#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1)
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#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4)
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#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2)
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#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8)
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#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3)
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/* Period and SnapShot Register for COUNTER_SIZE = 32 */
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/*----------------------------------------------------*/
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/* PERIODL register */
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#define ALTERA_AVALON_TIMER_PERIODL_REG 2
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#define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIODL_OFST (0)
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/* PERIODH register */
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#define ALTERA_AVALON_TIMER_PERIODH_REG 3
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#define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIODH_OFST (0)
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/* SNAPL register */
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#define ALTERA_AVALON_TIMER_SNAPL_REG 4
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#define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAPL_OFST (0)
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/* SNAPH register */
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#define ALTERA_AVALON_TIMER_SNAPH_REG 5
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#define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAPH_OFST (0)
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static uint32_t accumulated_cycle_count;
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static uint32_t get_snapshot(void)
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{
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#if TIMER_0_SNAPSHOT
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uint32_t snap, s1, s2;
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int key;
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key = irq_lock();
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/* Writing any data to one of the snapshot registers populates all
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* of them with the value of the counter. The data written is ignored
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*/
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_SNAPL_REG,
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1);
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s1 = _nios2_reg_read((void *)TIMER_0_BASE,
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ALTERA_AVALON_TIMER_SNAPL_REG) &
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ALTERA_AVALON_TIMER_SNAPL_MSK;
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s2 = _nios2_reg_read((void *)TIMER_0_BASE,
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ALTERA_AVALON_TIMER_SNAPH_REG) &
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ALTERA_AVALON_TIMER_SNAPH_MSK;
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irq_unlock(key);
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snap = s1 | (s2 << 16);
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return sys_clock_hw_cycles_per_tick - snap;
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#else
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return 0;
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#endif
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}
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static void timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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/* Clear the interrupt */
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_STATUS_REG,
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0);
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accumulated_cycle_count += sys_clock_hw_cycles_per_tick;
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_sys_clock_tick_announce();
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}
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#ifdef CONFIG_TICKLESS_IDLE
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#error "Tickless idle not yet implemented for Avalon timer"
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#endif
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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#if TIMER_0_FIXED_PERIOD
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#error "Can't set timer period!"
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#else
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_PERIODL_REG,
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sys_clock_hw_cycles_per_tick & 0xFFFF);
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_PERIODH_REG,
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(sys_clock_hw_cycles_per_tick >> 16) & 0xFFFF);
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#endif
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IRQ_CONNECT(TIMER_0_IRQ, 0, timer_irq_handler, NULL, 0);
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irq_enable(TIMER_0_IRQ);
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/* Initial configuration: Generate interrupts, run continuously,
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* start running
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*/
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_nios2_reg_write((void *)TIMER_0_BASE, ALTERA_AVALON_TIMER_CONTROL_REG,
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ALTERA_AVALON_TIMER_CONTROL_ITO_MSK |
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ALTERA_AVALON_TIMER_CONTROL_CONT_MSK |
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ALTERA_AVALON_TIMER_CONTROL_START_MSK);
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return 0;
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}
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uint32_t k_cycle_get_32(void)
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{
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return accumulated_cycle_count + get_snapshot();
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}
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