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zephyr/arch
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Martin Åberg feae3249b2 sparc: add support for thread local storage 
Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch. Register g7 is
used to point to the thread data. Thread data is accessed with negative
offsets from g7.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-11-13 14:53:55 -08:00
..
arc tracing: roll thread switch in/out into thread stats functions 2020-11-11 23:55:49 -05:00
arm arch: arm: push ssf to thread privileged stack to complete stack frame 2020-11-12 17:12:38 -05:00
common
nios2 nios2: fix register saving during thread switch instrumentation 2020-11-11 23:55:49 -05:00
posix tracing: roll thread switch in/out into thread stats functions 2020-11-11 23:55:49 -05:00
riscv tracing: roll thread switch in/out into thread stats functions 2020-11-11 23:55:49 -05:00
sparc sparc: add support for thread local storage 2020-11-13 14:53:55 -08:00
x86 tracing: roll thread switch in/out into thread stats functions 2020-11-11 23:55:49 -05:00
xtensa tracing: roll thread switch in/out into thread stats functions 2020-11-11 23:55:49 -05:00
CMakeLists.txt
Kconfig sparc: add support for thread local storage 2020-11-13 14:53:55 -08:00