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https://github.com/zephyrproject-rtos/zephyr
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e34f1cee06
Implement a set of per-cpu trampoline stacks which all interrupts and exceptions will initially land on, and also as an intermediate stack for privilege changes as we need some stack space to swap page tables. Set up the special trampoline page which contains all the trampoline stacks, TSS, and GDT. This page needs to be present in the user page tables or interrupts don't work. CPU exceptions, with KPTI turned on, are treated as interrupts and not traps so that we have IRQs locked on exception entry. Add some additional macros for defining IDT entries. Add special handling of locore text/rodata sections when creating user mode page tables on x86-64. Restore qemu_x86_64 to use KPTI, and remove restrictions on enabling user mode on x86-64. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
44 lines
1.1 KiB
C
44 lines
1.1 KiB
C
/*
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* Copyright (c) 2019 Intel Corp.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_
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#define ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_
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#include <arch/x86/mmustructs.h>
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#ifndef _ASMLANGUAGE
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/* linker symbols defining the bounds of the kernel part loaded in locore */
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extern char _locore_start[], _locore_end[];
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/*
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* Per-CPU bootstrapping parameters. See locore.S and cpu.c.
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*/
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struct x86_cpuboot {
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volatile int ready; /* CPU has started */
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u16_t tr; /* selector for task register */
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struct x86_tss64 *gs_base; /* Base address for GS segment */
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u64_t sp; /* initial stack pointer */
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arch_cpustart_t fn; /* kernel entry function */
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void *arg; /* argument for above function */
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#ifdef CONFIG_X86_MMU
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struct x86_page_tables *ptables; /* Runtime page tables to install */
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#endif /* CONFIG_X86_MMU */
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};
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typedef struct x86_cpuboot x86_cpuboot_t;
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extern u8_t x86_cpu_loapics[]; /* CPU logical ID -> local APIC ID */
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#endif /* _ASMLANGUAGE */
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#ifdef CONFIG_X86_KPTI
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#define Z_X86_TRAMPOLINE_STACK_SIZE 128
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#endif
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#endif /* ZEPHYR_ARCH_X86_INCLUDE_INTEL64_KERNEL_ARCH_DATA_H_ */
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