mirror of
https://github.com/zephyrproject-rtos/zephyr
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Updates the mcux drivers and device header files for the k64 from mcux 2.1 to mcux 2.2. Updates the k6x soc init and ethernet shim driver to reflect mcux interface changes. Origin: NXP MCUXpresso SDK 2.2 URL: mcux.nxp.com Maintained-by: External Change-Id: Icb578dddbe84c190e990b756193bef621010a898 Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
196 lines
6.3 KiB
C
196 lines
6.3 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_gpio.h"
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/*******************************************************************************
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* Variables
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******************************************************************************/
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static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
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static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the GPIO instance according to the GPIO base
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*
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* @param base GPIO peripheral base pointer(PTA, PTB, PTC, etc.)
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* @retval GPIO instance
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*/
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static uint32_t GPIO_GetInstance(GPIO_Type *base);
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t GPIO_GetInstance(GPIO_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_gpioBases); instance++)
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{
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if (s_gpioBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_gpioBases));
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return instance;
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}
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void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
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{
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assert(config);
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if (config->pinDirection == kGPIO_DigitalInput)
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{
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base->PDDR &= ~(1U << pin);
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}
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else
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{
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GPIO_WritePinOutput(base, pin, config->outputLogic);
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base->PDDR |= (1U << pin);
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}
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}
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uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
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{
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uint8_t instance;
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PORT_Type *portBase;
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instance = GPIO_GetInstance(base);
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portBase = s_portBases[instance];
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return portBase->ISFR;
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}
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void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
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{
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uint8_t instance;
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PORT_Type *portBase;
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instance = GPIO_GetInstance(base);
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portBase = s_portBases[instance];
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portBase->ISFR = mask;
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}
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#if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
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void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute)
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{
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base->GACR = ((uint32_t)attribute << GPIO_GACR_ACB0_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB1_SHIFT) |
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((uint32_t)attribute << GPIO_GACR_ACB2_SHIFT) | ((uint32_t)attribute << GPIO_GACR_ACB3_SHIFT);
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}
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#endif
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#if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
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/*******************************************************************************
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* Variables
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******************************************************************************/
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static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the FGPIO instance according to the GPIO base
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*
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* @param base FGPIO peripheral base pointer(PTA, PTB, PTC, etc.)
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* @retval FGPIO instance
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*/
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static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_fgpioBases); instance++)
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{
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if (s_fgpioBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_fgpioBases));
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return instance;
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}
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void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config)
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{
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assert(config);
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if (config->pinDirection == kGPIO_DigitalInput)
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{
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base->PDDR &= ~(1U << pin);
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}
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else
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{
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FGPIO_WritePinOutput(base, pin, config->outputLogic);
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base->PDDR |= (1U << pin);
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}
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}
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uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base)
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{
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uint8_t instance;
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instance = FGPIO_GetInstance(base);
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PORT_Type *portBase;
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portBase = s_portBases[instance];
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return portBase->ISFR;
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}
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void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask)
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{
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uint8_t instance;
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instance = FGPIO_GetInstance(base);
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PORT_Type *portBase;
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portBase = s_portBases[instance];
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portBase->ISFR = mask;
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}
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#if defined(FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER
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void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute)
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{
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base->GACR = (attribute << FGPIO_GACR_ACB0_SHIFT) | (attribute << FGPIO_GACR_ACB1_SHIFT) |
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(attribute << FGPIO_GACR_ACB2_SHIFT) | (attribute << FGPIO_GACR_ACB3_SHIFT);
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}
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#endif
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#endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
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