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https://github.com/zephyrproject-rtos/zephyr
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4d778b789a
This commit updates the `xilinx_zynqmp` SoC initialisation code to use the CMSIS-Core(R) features. In addition, it also defines the Core IP revision value for the SoC as specified in the Zynq UltraScale+ Device Technical Reference Manual. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
15 lines
222 B
C
15 lines
222 B
C
/*
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* Copyright (c) 2019 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#ifndef _BOARD__H_
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#define _BOARD__H_
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/* Define CMSIS configurations */
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#define __CR_REV 1U
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#endif /* _BOARD__H_ */
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