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https://github.com/zephyrproject-rtos/zephyr
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Necessary for supporting for EastRising 0.42 OLED display/board. Some boards don't have external Iref set up. This is probably done in an effort to save on component cost. This command is only documented in the V1.1 revision of the SSD1306 datasheet. See issue https://github.com/olikraus/u8g2/issues/1047 Signed-off-by: Théo Battrel <theo.battrel@nordicsemi.no>
123 lines
3.4 KiB
C
123 lines
3.4 KiB
C
/*
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* Copyright (c) 2018 Phytec Messtechnik GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __SSD1306_REGS_H__
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#define __SSD1306_REGS_H__
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/* All following bytes will contain commands */
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#define SSD1306_CONTROL_ALL_BYTES_CMD 0x00
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/* All following bytes will contain data */
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#define SSD1306_CONTROL_ALL_BYTES_DATA 0x40
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/* The next byte will contain a command */
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#define SSD1306_CONTROL_BYTE_CMD 0x80
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/* The next byte will contain data */
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#define SSD1306_CONTROL_BYTE_DATA 0xc0
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#define SSD1306_READ_STATUS_MASK 0xc0
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#define SSD1306_READ_STATUS_BUSY 0x80
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#define SSD1306_READ_STATUS_ON 0x40
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/*
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* Fundamental Command Table
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*/
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#define SSD1306_SET_CONTRAST_CTRL 0x81 /* double byte command */
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#define SSD1306_SET_ENTIRE_DISPLAY_OFF 0xa4
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#define SSD1306_SET_ENTIRE_DISPLAY_ON 0xa5
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/* RAM data of 1 indicates an "ON" pixel */
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#define SSD1306_SET_NORMAL_DISPLAY 0xa6
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/* RAM data of 0 indicates an "ON" pixel */
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#define SSD1306_SET_REVERSE_DISPLAY 0xa7
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#define SSD1306_DISPLAY_OFF 0xae
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#define SSD1306_DISPLAY_ON 0xaf
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/*
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* Addressing Setting Command Table
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*/
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#define SSD1306_SET_LOWER_COL_ADDRESS 0x00
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#define SSD1306_SET_LOWER_COL_ADDRESS_MASK 0x0f
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#define SSD1306_SET_HIGHER_COL_ADDRESS 0x10
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#define SSD1306_SET_HIGHER_COL_ADDRESS_MASK 0x0f
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#define SSD1306_SET_MEM_ADDRESSING_MODE 0x20 /* double byte command */
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#define SSD1306_SET_MEM_ADDRESSING_HORIZONTAL 0x00
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#define SSD1306_SET_MEM_ADDRESSING_VERTICAL 0x01
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#define SSD1306_SET_MEM_ADDRESSING_PAGE 0x02
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#define SSD1306_SET_COLUMN_ADDRESS 0x21 /* triple byte command */
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#define SSD1306_SET_PAGE_ADDRESS 0x22 /* triple byte command */
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#define SSD1306_SET_PAGE_START_ADDRESS 0xb0
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#define SSD1306_SET_PAGE_START_ADDRESS_MASK 0x07
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/*
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* Hardware Configuration Command Table
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*/
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#define SSD1306_SET_START_LINE 0x40
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#define SSD1306_SET_START_LINE_MASK 0x3f
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#define SSD1306_SET_SEGMENT_MAP_NORMAL 0xa0
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#define SSD1306_SET_SEGMENT_MAP_REMAPED 0xa1
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#define SSD1306_SET_MULTIPLEX_RATIO 0xa8 /* double byte command */
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#define SSD1306_SET_COM_OUTPUT_SCAN_NORMAL 0xc0
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#define SSD1306_SET_COM_OUTPUT_SCAN_FLIPPED 0xc8
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#define SSD1306_SET_DISPLAY_OFFSET 0xd3 /* double byte command */
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#define SSD1306_SET_PADS_HW_CONFIG 0xda /* double byte command */
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#define SSD1306_SET_PADS_HW_SEQUENTIAL 0x02
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#define SSD1306_SET_PADS_HW_ALTERNATIVE 0x12
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#define SSD1306_SET_IREF_MODE 0xad
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#define SSD1306_SET_IREF_MODE_INTERNAL 0x30
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#define SSD1306_SET_IREF_MODE_EXTERNAL 0x00
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/*
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* Timing and Driving Scheme Setting Command Table
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*/
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#define SSD1306_SET_CLOCK_DIV_RATIO 0xd5 /* double byte command */
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#define SSD1306_SET_CHARGE_PERIOD 0xd9 /* double byte command */
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#define SSD1306_SET_VCOM_DESELECT_LEVEL 0xdb /* double byte command */
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#define SSD1306_NOP 0xe3
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/*
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* Charge Pump Command Table
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*/
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#define SSD1306_SET_CHARGE_PUMP_ON 0x8d /* double byte command */
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#define SSD1306_SET_CHARGE_PUMP_ON_DISABLED 0x10
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#define SSD1306_SET_CHARGE_PUMP_ON_ENABLED 0x14
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#define SH1106_SET_DCDC_MODE 0xad /* double byte command */
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#define SH1106_SET_DCDC_DISABLED 0x8a
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#define SH1106_SET_DCDC_ENABLED 0x8b
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#define SSD1306_SET_PUMP_VOLTAGE_64 0x30
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#define SSD1306_SET_PUMP_VOLTAGE_74 0x31
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#define SSD1306_SET_PUMP_VOLTAGE_80 0x32
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#define SSD1306_SET_PUMP_VOLTAGE_90 0x33
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/*
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* Read modify write
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*/
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#define SSD1306_READ_MODIFY_WRITE_START 0xe0
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#define SSD1306_READ_MODIFY_WRITE_END 0xee
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/* time constants in ms */
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#define SSD1306_RESET_DELAY 1
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#endif
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