zephyr/dts/bindings/cpu
Kumar Gala 4192254ef2 dts: nios2: Add interrupt controller support in dts
Added properties to support the core interrupt controller on the NIOS2
cpu cores and enable that support for the NS16550 UART.

We rename some compatibles so that the cpu core compatibles is unique.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-03-27 15:16:53 -05:00
..
altera,nios2f.yaml dts: nios2: Add interrupt controller support in dts 2020-03-27 15:16:53 -05:00
arm,cortex-a53.yaml
arm,cortex-m3.yaml
arm,cortex-m4.yaml
arm,cortex-m4f.yaml
arm,cortex-m7.yaml
arm,cortex-m23.yaml
arm,cortex-m33.yaml
arm,cortex-m0.yaml
arm,cortex-m0+.yaml
arm,cortex-r4.yaml
arm,cortex-r4f.yaml
arm,cortex-r5.yaml
arm,cortex-r5f.yaml
cadence,tensilica-xtensa-lx4.yaml dts: cpu: add binding for Cadence Tensilica Xtensa LX4 CPU 2020-02-05 10:43:25 -05:00
cadence,tensilica-xtensa-lx6.yaml
cpu.yaml
qemu,nios2-zephyr.yaml dts: nios2: Add interrupt controller support in dts 2020-03-27 15:16:53 -05:00
sample_controller.yaml
snps,arcem.yaml