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https://github.com/zephyrproject-rtos/zephyr
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ed9cb841c3
Refactors all of the clock control drivers to use a shared driver class initialization priority configuration, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control drivers separately from other devices. This is similar to other driver classes like I2C and SPI. Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new option is the lower of the two, which means earlier initialization. The even lower defaults for STM32 and Arm Beetle are preserved by SoC-family level overrides. Signed-off-by: Maureen Helm <maureen.helm@intel.com>
86 lines
2.0 KiB
C
86 lines
2.0 KiB
C
/*
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* Copyright (c) 2019 Vestas Wind Systems A/S
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*
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* Based on clock_control_rv32m1_pcc.c, which is:
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* Copyright (c) 2018 Foundries.io
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_kinetis_pcc
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#include <errno.h>
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <fsl_clock.h>
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(clock_control_mcux_pcc);
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struct mcux_pcc_config {
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uint32_t base_address;
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};
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#define DEV_CFG(dev) ((struct mcux_pcc_config *)(dev->config))
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#define DEV_BASE(dev) (DEV_CFG(dev)->base_address)
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#ifndef MAKE_PCC_REGADDR
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#define MAKE_PCC_REGADDR(base, offset) ((base) + (offset))
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#endif
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static inline clock_ip_name_t clock_ip(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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uint32_t offset = POINTER_TO_UINT(sub_system);
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return MAKE_PCC_REGADDR(DEV_BASE(dev), offset);
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}
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static int mcux_pcc_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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CLOCK_EnableClock(clock_ip(dev, sub_system));
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return 0;
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}
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static int mcux_pcc_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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CLOCK_DisableClock(clock_ip(dev, sub_system));
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return 0;
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}
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static int mcux_pcc_get_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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*rate = CLOCK_GetIpFreq(clock_ip(dev, sub_system));
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return 0;
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}
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static int mcux_pcc_init(const struct device *dev)
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{
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return 0;
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}
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static const struct clock_control_driver_api mcux_pcc_api = {
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.on = mcux_pcc_on,
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.off = mcux_pcc_off,
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.get_rate = mcux_pcc_get_rate,
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};
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#define MCUX_PCC_INIT(inst) \
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static const struct mcux_pcc_config mcux_pcc##inst##_config = { \
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.base_address = DT_INST_REG_ADDR(inst) \
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}; \
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\
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DEVICE_DT_INST_DEFINE(inst, \
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&mcux_pcc_init, \
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NULL, \
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NULL, &mcux_pcc##inst##_config, \
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PRE_KERNEL_1, \
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
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&mcux_pcc_api);
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DT_INST_FOREACH_STATUS_OKAY(MCUX_PCC_INIT)
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