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https://github.com/zephyrproject-rtos/zephyr
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For now we've used range properties as a pass through. However range properties can translate from one address space to another. This is typically used one address spaces translate from one physical bus to another (For example going from PCI address space to internal SoC memory map). However, we can also use this for cases where we want to reduce duplication (For example with ARMv8-M for secure v non-secure MMIO registers). 'ranges' takes either the form of: ranges; /* pass through translation */ or: ranges = <child-bus-address parent-bus-address length>; Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
106 lines
3.4 KiB
Python
106 lines
3.4 KiB
Python
#
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# Copyright (c) 2018 Bobby Noelte
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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from extract.globals import *
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from extract.directive import DTDirective
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##
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# @brief Manage reg directive.
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#
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class DTReg(DTDirective):
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def __init__(self):
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pass
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##
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# @brief Extract reg directive info
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#
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# @param node_address Address of node owning the
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# reg definition.
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# @param yaml YAML definition for the owning node.
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# @param names (unused)
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# @param def_label Define label string of node owning the
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# compatible definition.
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#
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def extract(self, node_address, yaml, names, def_label, div):
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node = reduced[node_address]
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node_compat = get_compat(node_address)
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reg = reduced[node_address]['props']['reg']
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if type(reg) is not list: reg = [ reg, ]
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(nr_address_cells, nr_size_cells) = get_addr_size_cells(node_address)
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# generate defines
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post_label = "BASE_ADDRESS"
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if def_label not in regs_config.values():
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if yaml[node_compat].get('use-property-label', False):
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label = node['props'].get('label', None)
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if label:
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post_label = label
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l_base = def_label.split('/')
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l_addr = [convert_string_to_label(post_label)]
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l_size = ["SIZE"]
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index = 0
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props = list(reg)
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while props:
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prop_def = {}
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prop_alias = {}
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addr = 0
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size = 0
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# Check is defined should be indexed (_0, _1)
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if index == 0 and len(props) < 3:
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# 1 element (len 2) or no element (len 0) in props
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l_idx = []
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else:
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l_idx = [str(index)]
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try:
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name = [names.pop(0).upper()]
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except:
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name = []
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for x in range(nr_address_cells):
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addr += props.pop(0) << (32 * (nr_address_cells - x - 1))
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for x in range(nr_size_cells):
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size += props.pop(0) << (32 * (nr_size_cells - x - 1))
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addr += translate_addr(addr, node_address,
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nr_address_cells, nr_size_cells)
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l_addr_fqn = '_'.join(l_base + l_addr + l_idx)
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l_size_fqn = '_'.join(l_base + l_size + l_idx)
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if nr_address_cells:
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prop_def[l_addr_fqn] = hex(addr)
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if nr_size_cells:
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prop_def[l_size_fqn] = int(size / div)
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if len(name):
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if nr_address_cells:
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prop_alias['_'.join(l_base + name + l_addr)] = l_addr_fqn
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if nr_size_cells:
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prop_alias['_'.join(l_base + name + l_size)] = l_size_fqn
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# generate defs for node aliases
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if node_address in aliases:
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for i in aliases[node_address]:
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alias_label = convert_string_to_label(i)
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alias_addr = [alias_label] + l_addr + l_idx
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alias_size = [alias_label] + l_size + l_idx
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prop_alias['_'.join(alias_addr)] = '_'.join(l_base + l_addr + l_idx)
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prop_alias['_'.join(alias_size)] = '_'.join(l_base + l_size + l_idx)
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insert_defs(node_address, prop_def, prop_alias)
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# increment index for definition creation
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index += 1
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##
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# @brief Management information for registers.
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reg = DTReg()
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