mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-10 03:55:52 +00:00
d8b5a81c67
Add devicetree bindings for the Xilinx AXI GPIO v2 IP. This GPIO controller has an optional "GPIO2" port, which is not always present. The Xilinx specific devicetree property names and their meaning match a subset of what can automatically be generated based on the FPGA logic design using https://github.com/Xilinx/device-tree-xlnx. These properties are also used by the Linux kernel. Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk> |
||
|---|---|---|
| .. | ||
| arc | ||
| arm | ||
| bindings | ||
| common | ||
| nios2 | ||
| posix | ||
| riscv | ||
| x86 | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||