Ulf Magnusson 5d0db517b9 dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values ... Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0 binding. The new binding adds a required riscv,ndev property, which gives the number of external interrupts supported. Use the new binding for microsemi-miv.dtsi (with a value of 31 for riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf) and riscv32-fe310.dtsi (which already assigns riscv,ndev). Also remove a spurious riscv,ndev assignment from riscv32-litex-vexriscv.dtsi. Also make edtlib and the old scripts/dts/ scripts replace '.' in compatible strings with '_' when generating identifiers. Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>		2019-08-02 11:44:09 +02:00
..
arc	arch: arc: optimize the float support	2019-08-01 18:09:35 -07:00
arm	soc : arm : microchip_mec Fix MEC1501 SoC ECIA initialization	2019-08-01 21:58:54 +03:00
nios2
posix
riscv32	dts: riscv: Add sifive,plic-1.0.0 binding and fix riscv,ndev values	2019-08-02 11:44:09 +02:00
x86	boards: remove quarl_se_c1000	2019-07-29 21:30:25 -07:00
x86_64/x86_64
xtensa
Kconfig