mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-03 16:01:56 +00:00
51ccb58dbb
Converted over all STM32F1 based boards to use device tree and removed
associated bits that now come from the device tree for STM32F1. Also
renamed the STM32F10{3,7} SoC dtsi to try and make it clear that the 'X'
is a place holder. Fixedup the top level compatiables in the boards to
be the specific 'X' instead of the generic one.
Boards that are now using devicetree:
* Nucleo f103rb
* STM3210C Eval
* STM32 MINI A15
Change-Id: I29b3634ec7451f974687d55980414efa655e2e96
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
64 lines
1.7 KiB
Plaintext
64 lines
1.7 KiB
Plaintext
# Zephyr Kernel Configuration
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CONFIG_ARM=y
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CONFIG_ARCH="arm"
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CONFIG_SOC_SERIES="stm32f1"
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CONFIG_SOC_FAMILY="st_stm32"
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CONFIG_BOARD="stm3210c_eval"
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CONFIG_SOC_SERIES_STM32F1X=y
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# Platform Configuration
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CONFIG_SOC_FAMILY_STM32=y
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CONFIG_SOC_STM32F107XC=y
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CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE=y
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CONFIG_BOARD_STM3210C_EVAL=y
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# General Kernel Options
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CONFIG_CORTEX_M_SYSTICK=y
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# 72MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# Serial Drivers
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CONFIG_SERIAL=y
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CONFIG_SERIAL_HAS_DRIVER=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_UART_STM32=y
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# enable USART2 - passthrough to STLINK v2 connector
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CONFIG_UART_STM32_PORT_2=y
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# enable console on this port by default
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_2"
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# Pinmux Driver
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CONFIG_PINMUX=y
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CONFIG_PINMUX_STM32=y
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# GPIO Controller
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CONFIG_GPIO=y
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CONFIG_GPIO_STM32=y
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CONFIG_GPIO_STM32_PORTA=y
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CONFIG_GPIO_STM32_PORTB=y
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CONFIG_GPIO_STM32_PORTC=y
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# RCC configuration
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL_STM32F10X=n
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CONFIG_CLOCK_CONTROL_STM32F10X_CONN_LINE=y
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CONFIG_CLOCK_STM32F10X_CONN_LINE_SYSCLK_SRC_PLLCLK=y
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# use PREDIV1 as PLL input
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CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_SRC_PREDIV1=y
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# however, the board does not have an external oscillator, so just use
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# the 8MHz clock signal coming from integrated STLink
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CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1_SRC_HSE=y
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CONFIG_CLOCK_STM32F10X_CONN_LINE_HSE_BYPASS=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32F10X_CONN_LINE_PREDIV1=0
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CONFIG_CLOCK_STM32F10X_CONN_LINE_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32F10X_CONN_LINE_AHB_PRESCALER=0
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# APB1 clock must not to exceed 36MHz limit
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CONFIG_CLOCK_STM32F10X_CONN_LINE_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32F10X_CONN_LINE_APB2_PRESCALER=0
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#enable DTS
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CONFIG_HAS_DTS=y
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