mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-08-15 04:15:21 +00:00
4eb6aab3ad
Now for x86 platforms, UART is configured statically or dynamically into the driver and not anymore in the board's system.c. Thus limiting the information to be scattered into 2 files instead of 3. Then in future, it will also be possible to remove driver specific informations from the generic UART API structure. Change-Id: I7b7fa37f10f88316a4d375c99de3bbacf152a3e3 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
320 lines
8.9 KiB
C
320 lines
8.9 KiB
C
/* board.h - board configuration macros for the 'Quark' BSP */
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/*
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* Copyright (c) 2013-2015, Wind River Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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DESCRIPTION
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This header file is used to specify and describe board-level aspects for
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the 'Quark' BSP.
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*/
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#ifndef __INCboardh
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#define __INCboardh
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#include <misc/util.h>
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#ifndef _ASMLANGUAGE
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#include <drivers/rand32.h>
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#endif
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#define N_PIC_IRQS 16 /* number of PIC IRQs */
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#define INT_VEC_IRQ0 0x20 /* Vector number for IRQ0 */
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/*
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* IO APIC (IOAPIC) device information (Intel ioapic)
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*/
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#define IOAPIC_NUM_RTES 24 /* Number of IRQs = 24 */
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#define IOAPIC_BASE_ADRS_PHYS 0xFEC00000 /* base physical address */
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#define IOAPIC_SIZE KB(4)
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#define IOAPIC_BASE_ADRS IOAPIC_BASE_ADRS_PHYS
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/*
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* Local APIC (LOAPIC) device information (Intel loapic)
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*/
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#define LOAPIC_BASE_ADRS_PHYS 0xFEE00000 /* base physical address */
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#define LOAPIC_SIZE KB(4)
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#define LOAPIC_BASE_ADRS LOAPIC_BASE_ADRS_PHYS
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/*
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* HPET device information
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*/
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#define HPET_BASE_ADRS_PHYS 0xFED00000
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#define HPET_SIZE KB(4)
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#define HPET_BASE_ADRS HPET_BASE_ADRS_PHYS
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#define HPET_TIMER0_IRQ (20)
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#define HPET_TIMER0_VEC (HPET_TIMER0_IRQ + INT_VEC_IRQ0)
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/* HPET uses falling edge triggered interrupt */
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#define HPET_IOAPIC_FLAGS (IOAPIC_EDGE | IOAPIC_LOW)
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/* serial port (aka COM port) information */
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#define COM1_BAUD_RATE 115200
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#define COM1_PCI_IDX 2
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#define COM2_BAUD_RATE 115200
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#define COM2_PCI_IDX 0
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#define COM2_INT_LVL 0x11 /* COM2 connected to IRQ17 */
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#define UART_REG_ADDR_INTERVAL 4 /* address diff of adjacent regs. */
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#define UART_XTAL_FREQ (2764800 * 16)
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/* UART uses level triggered interrupt, low level */
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#define UART_IOAPIC_FLAGS (IOAPIC_LEVEL | IOAPIC_LOW)
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/* uart configuration settings */
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/* Generic definitions */
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#define CONFIG_UART_PCI_VENDOR_ID 0x8086
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#define CONFIG_UART_PCI_DEVICE_ID 0x0936
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#define CONFIG_UART_NUM_SYSTEM_PORTS 2
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#define CONFIG_UART_NUM_EXTRA_PORTS 0
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#define CONFIG_UART_BAUDRATE COM1_BAUD_RATE
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#define CONFIG_UART_NUM_PORTS \
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(CONFIG_UART_NUM_SYSTEM_PORTS + CONFIG_UART_NUM_EXTRA_PORTS)
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/* Console definitions */
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#define CONFIG_UART_CONSOLE_INDEX 0
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#define CONFIG_UART_CONSOLE_PCI_IDX COM1_PCI_IDX
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/*
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* The irq_connect() API connects to a (virtualized) IRQ and the
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* associated interrupt controller is programmed with the allocated vector.
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* The Quark board virtualizes IRQs as follows:
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*
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* - The first IOAPIC_NUM_RTES IRQs are provided by the IOAPIC
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* - The remaining IRQs are provided by the LOAPIC.
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*
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* Thus, for example, if the IOAPIC supports 24 IRQs:
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*
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* - IRQ0 to IRQ23 map to IOAPIC IRQ0 to IRQ23
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* - IRQ24 to IRQ29 map to LOAPIC LVT entries as follows:
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*
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* IRQ24 -> LOAPIC_TIMER
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* IRQ25 -> LOAPIC_THERMAL
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* IRQ26 -> LOAPIC_PMC
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* IRQ27 -> LOAPIC_LINT0
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* IRQ28 -> LOAPIC_LINT1
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* IRQ29 -> LOAPIC_ERROR
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*/
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#define LOAPIC_VEC_BASE(x) (x + INT_VEC_IRQ0 + IOAPIC_NUM_RTES)
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#ifndef _ASMLANGUAGE
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/*
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* The <pri> parameter is deliberately ignored. For this BSP, the macro just has
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* to make sure that unique vector numbers are generated.
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*/
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#define SYS_INT_REGISTER(s, irq, pri) \
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NANO_CPU_INT_REGISTER(s, INT_VEC_IRQ0 + (irq), 0)
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#endif
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/* PCI definitions */
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#define PCI_BUS_NUMBERS 2
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#define PCI_CTRL_ADDR_REG 0xCF8
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#define PCI_CTRL_DATA_REG 0xCFC
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#define PCI_INTA 1
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#define PCI_INTB 2
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#define PCI_INTC 3
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#define PCI_INTD 4
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#ifndef _ASMLANGUAGE
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/*
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* Device drivers utilize the macros PLB_BYTE_REG_WRITE() and
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* PLB_BYTE_REG_READ() to access byte-wide registers on the processor
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* local bus (PLB), as opposed to a PCI bus, for example. Boards are
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* expected to provide implementations of these macros.
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*/
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#define PLB_BYTE_REG_WRITE(data, address) \
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sys_out8(data, (unsigned int)address)
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#define PLB_BYTE_REG_READ(address) sys_in8((unsigned int)address)
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/*******************************************************************************
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*
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* outByte - output byte to memory location
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*
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* RETURNS: N/A
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*
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* NOMANUAL
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*/
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static inline void outByte(uint8_t data, uint32_t addr)
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{
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*(volatile uint8_t *)addr = data;
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}
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/*******************************************************************************
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*
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* inByte - obtain byte value from memory location
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*
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* This function issues the 'move' instruction to read a byte from the specified
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* memory address.
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*
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* RETURNS: the byte read from the specified memory address
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*
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* NOMANUAL
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*/
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static inline uint8_t inByte(uint32_t addr)
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{
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return *((volatile uint8_t *)addr);
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}
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/*
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* Device drivers utilize the macros PLB_WORD_REG_WRITE() and
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* PLB_WORD_REG_READ() to access shortword-wide registers on the processor
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* local bus (PLB), as opposed to a PCI bus, for example. Boards are
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* expected to provide implementations of these macros.
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*/
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#define PLB_WORD_REG_WRITE(data, address) \
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sys_out16(data, (unsigned int)address)
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#define PLB_WORD_REG_READ(address) sys_in16((unsigned int)address)
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/*******************************************************************************
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*
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* outWord - output word to memory location
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*
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* RETURNS: N/A
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*
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* NOMANUAL
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*/
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static inline void outWord(uint16_t data, uint32_t addr)
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{
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*(volatile uint16_t *)addr = data;
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}
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/*******************************************************************************
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*
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* inWord - obtain word value from memory location
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*
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* This function issues the 'move' instruction to read a word from the specified
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* memory address.
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*
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* RETURNS: the word read from the specified memory address
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*
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* NOMANUAL
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*/
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static inline uint16_t inWord(uint32_t addr)
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{
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return *((volatile uint16_t *)addr);
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}
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/*
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* Device drivers utilize the macros PLB_LONG_REG_WRITE() and
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* PLB_LONG_REG_READ() to access longword-wide registers on the processor
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* local bus (PLB), as opposed to a PCI bus, for example. Boards are
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* expected to provide implementations of these macros.
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*/
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#define PLB_LONG_REG_WRITE(data, address) \
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sys_out32(data, (unsigned int)address)
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#define PLB_LONG_REG_READ(address) sys_in32((unsigned int)address)
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/*******************************************************************************
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*
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* outLong - output long word to memory location
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*
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* RETURNS: N/A
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*
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* NOMANUAL
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*/
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static inline void outLong(uint32_t data, uint32_t addr)
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{
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*(volatile uint32_t *)addr = data;
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}
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/*******************************************************************************
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*
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* inLong - obtain long word value from memory location
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*
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* This function issues the 'move' instruction to read a word from the specified
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* memory address.
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*
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* RETURNS: the long word read from the specified memory address
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*
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* NOMANUAL
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*/
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static inline uint32_t inLong(uint32_t addr)
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{
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return *((volatile uint32_t *)addr);
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}
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#endif /* !_ASMLANGUAGE */
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/*******************************************************************************
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*
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* pci_pin2irq - convert PCI interrupt PIN to IRQ
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*
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* The routine uses "standard design consideration" and implies that
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* INTA (pin 1) -> IRQ 16
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* INTB (pin 2) -> IRQ 17
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* INTC (pin 3) -> IRQ 18
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* INTD (pin 4) -> IRQ 19
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*
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* RETURNS: IRQ number, -1 if the result is incorrect
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*
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*/
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static inline int pci_pin2irq(int pin)
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{
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if ((pin < PCI_INTA) || (pin > PCI_INTD))
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return -1;
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return N_PIC_IRQS + pin - 1;
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}
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/*******************************************************************************
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*
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* pci_irq2pin - convert IRQ to PCI interrupt pin
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*
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* RETURNS: pin number, -1 if the result is incorrect
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*
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*/
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static inline int pci_irq2pin(int irq)
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{
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if ((irq < N_PIC_IRQS) || (irq > N_PIC_IRQS + PCI_INTD - 1))
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return -1;
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return irq - N_PIC_IRQS + 1;
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}
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extern void _SysIntVecProgram(unsigned int vector, unsigned int);
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#endif /* __INCboardh */
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