mirror of
https://github.com/zephyrproject-rtos/zephyr
synced 2025-09-02 03:22:30 +00:00
1f4b5ddd0f
With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
81 lines
2.2 KiB
ArmAsm
81 lines
2.2 KiB
ArmAsm
/*
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* Copyright (c) 2018 Foundries.io Ltd
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <toolchain.h>
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/* Imports */
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GTEXT(__initialize)
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GTEXT(__irq_wrapper)
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/* Exports */
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GTEXT(__start)
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/*
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* Interrupts work the same way for both the RI5CY and ZERO-RISCY cores
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* in this SoC; the only difference is the location of the vectors section
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* on flash. We thus reuse this ivt definition for each core.
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*
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* On interrupt, the event unit sets pc to the address in this table
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* at byte offset 4 * (IRQ line number).
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*
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* The reset, illegal instruction, ecall, and load store unit error exceptions
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* are handled by the addresses right after the IRQ table.
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*
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* Note: Per RV32I restrictions, "j SOME_HANDLER" can jump within a +/- 1MiB
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* range. This is not a problem on this SoC: RI5CY is allocated 1MiB flash
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* and ZERO-RISCY is allocated 256 KiB, and these flash banks contain the
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* text and vectors sections, so the limits are satisfied.
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*/
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SECTION_FUNC(vectors, ivt)
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.option norvc
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/* Interrupts */
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j __irq_wrapper /* IRQ 0 */
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j __irq_wrapper /* IRQ 1 */
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j __irq_wrapper /* IRQ 2 */
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j __irq_wrapper /* IRQ 3 */
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j __irq_wrapper /* IRQ 4 */
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j __irq_wrapper /* IRQ 5 */
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j __irq_wrapper /* IRQ 6 */
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j __irq_wrapper /* IRQ 7 */
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j __irq_wrapper /* IRQ 8 */
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j __irq_wrapper /* IRQ 9 */
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j __irq_wrapper /* IRQ 10 */
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j __irq_wrapper /* IRQ 11 */
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j __irq_wrapper /* IRQ 12 */
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j __irq_wrapper /* IRQ 13 */
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j __irq_wrapper /* IRQ 14 */
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j __irq_wrapper /* IRQ 15 */
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j __irq_wrapper /* IRQ 16 */
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j __irq_wrapper /* IRQ 17 */
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j __irq_wrapper /* IRQ 18 */
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j __irq_wrapper /* IRQ 19 */
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j __irq_wrapper /* IRQ 20 */
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j __irq_wrapper /* IRQ 21 */
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j __irq_wrapper /* IRQ 22 */
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j __irq_wrapper /* IRQ 23 */
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j __irq_wrapper /* IRQ 24 */
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j __irq_wrapper /* IRQ 25 */
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j __irq_wrapper /* IRQ 26 */
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j __irq_wrapper /* IRQ 27 */
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j __irq_wrapper /* IRQ 28 */
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j __irq_wrapper /* IRQ 29 */
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j __irq_wrapper /* IRQ 30 */
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j __irq_wrapper /* IRQ 31 */
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/* Exceptions */
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j __start /* reset */
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j __irq_wrapper /* illegal instruction */
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j __irq_wrapper /* ecall */
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j __irq_wrapper /* load store eunit error */
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SECTION_FUNC(vectors, __start)
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/* Set mtvec to point at ivt. */
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la t0, ivt
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csrw 0x305, t0
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/* Call into Zephyr initialization. */
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tail __initialize
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