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https://github.com/zephyrproject-rtos/zephyr
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a9183cd518
The STM32L4x SoCs embeds a slightly different embedded flash controller from the STM32F4x SoCs. This particular controller has the following properties : - Up to 2 512KiB banks divided in 2KiB pages - Flash can be accessed in any sizes - Flash must be written in 64bit aligned 64bit double-words The drivers/flash/flash_stm32f4x.c is refactored into a new common drivers/flash/flash_stm32.c and drivers/flash/flash_stm32l4x.c is created with the STM32L4x specific functions. To ease the refactoring and keep common functions, the STM32L4x flash headers are slightly modified to match the hardware reference naming and solve compilation issues. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
112 lines
2.1 KiB
C
112 lines
2.1 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <device.h>
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#include <string.h>
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#include <flash.h>
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#include <init.h>
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#include <soc.h>
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#include <flash_stm32.h>
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bool flash_stm32_valid_range(off_t offset, u32_t len)
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{
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return offset >= 0 && (offset + len - 1 <= STM32F4X_FLASH_END);
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}
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static int write_byte(off_t offset, u8_t val, struct flash_stm32_priv *p)
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{
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struct stm32f4x_flash *regs = p->regs;
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u32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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}
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rc = flash_stm32_wait_flash_idle(p);
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if (rc < 0) {
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return rc;
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}
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regs->cr &= ~CR_PSIZE_MASK;
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regs->cr |= FLASH_PSIZE_BYTE;
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regs->cr |= FLASH_CR_PG;
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/* flush the register write */
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tmp = regs->cr;
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*((u8_t *) offset + CONFIG_FLASH_BASE_ADDRESS) = val;
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rc = flash_stm32_wait_flash_idle(p);
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regs->cr &= (~FLASH_CR_PG);
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return rc;
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}
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static int erase_sector(u16_t sector, struct flash_stm32_priv *p)
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{
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struct stm32f4x_flash *regs = p->regs;
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u32_t tmp;
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int rc;
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/* if the control register is locked, do not fail silently */
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if (regs->cr & FLASH_CR_LOCK) {
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return -EIO;
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}
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rc = flash_stm32_wait_flash_idle(p);
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if (rc < 0) {
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return rc;
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}
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regs->cr &= STM32F4X_SECTOR_MASK;
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regs->cr |= FLASH_CR_SER | (sector << 3);
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regs->cr |= FLASH_CR_STRT;
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/* flush the register write */
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tmp = regs->cr;
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rc = flash_stm32_wait_flash_idle(p);
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regs->cr &= ~(FLASH_CR_SER | FLASH_CR_SNB);
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return rc;
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}
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int flash_stm32_block_erase_loop(unsigned int offset, unsigned int len,
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struct flash_stm32_priv *p)
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{
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int i, rc = 0;
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i = stm32f4x_get_sector(offset);
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for (; i <= stm32f4x_get_sector(offset + len - 1); i++) {
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rc = erase_sector(i, p);
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if (rc < 0) {
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break;
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}
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}
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return rc;
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}
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int flash_stm32_write_range(unsigned int offset, const void *data,
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unsigned int len, struct flash_stm32_priv *p)
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{
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int i, rc = 0;
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for (i = 0; i < len; i++, offset++) {
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rc = write_byte(offset, ((const u8_t *) data)[i], p);
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if (rc < 0) {
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return rc;
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}
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}
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return rc;
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}
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