Leandro Pereira 510e5d7ced arch: xtensa: Use the alternate _Level4Vector routine on ESP32 ... For some reason, the ESP32 HAL defines XCHAL_EXCM_LEVEL to 3. This enables a version of _Level4Vector that doesn't work on this hardware. Without complete visibility if the version that should work be axed, keep both in the tree, but build the working other version instead if building for ESP32. Jira: ZEP-2556 Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>		2017-08-25 15:31:46 -04:00
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offsets
startup	xtensa: optionally build reset vector code	2017-05-12 12:56:12 -04:00
atomic.S
cpu_idle.c	xtensa: use inline assembly instead of XT_* macros	2017-05-11 16:51:56 -04:00
crt1.S	xtensa: merge crt1-*.S	2017-05-12 12:56:12 -04:00
fatal.c	stack_sentinel: hang system on failure	2017-06-08 13:49:36 -05:00
irq_manage.c	arch: convert to using newly introduced integer sized types	2017-04-21 12:08:12 +00:00
irq_offload.c
Makefile	arch: xtensa: Convert Xtensa port to use gen_isr_table	2017-08-09 12:26:14 -07:00
swap.S	stack_sentinel: change cooperative check	2017-06-08 13:49:36 -05:00
thread.c	kernel: introduce opaque data type for stacks	2017-08-01 16:43:15 -07:00
xt_zephyr.S	debug: add stack sentinel feature	2017-05-13 15:14:41 -04:00
xtensa_context.S
xtensa_intr_asm.S	arch: xtensa: Move exception table to xtensa_intr.c	2017-08-09 12:26:14 -07:00
xtensa_intr.c	arch: xtensa: Move exception table to xtensa_intr.c	2017-08-09 12:26:14 -07:00
xtensa_vectors.S	arch: xtensa: Use the alternate _Level4Vector routine on ESP32	2017-08-25 15:31:46 -04:00