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https://github.com/zephyrproject-rtos/zephyr
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dd3ee06af7
Add gpio support for STM32G0X SoC series. Signed-off-by: Philippe Retornaz <philippe@shapescale.com> Signed-off-by: Francois Ramu <francois.ramu@st.com> # Conflicts: # drivers/gpio/gpio_stm32.h
131 lines
2.6 KiB
Plaintext
131 lines
2.6 KiB
Plaintext
/*
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* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
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* Copyright (c) 2019 ST Microelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/g0/stm32g0-pinctrl.dtsi>
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#include <arm/armv6-m.dtsi>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0+";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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soc {
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flash-controller@40022000 {
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compatible = "st,stm32g0-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x40022000 0x400>;
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interrupts = <3 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <8>;
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erase-block-size = <2048>;
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};
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};
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rcc: rcc@40021000 {
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compatible = "st,stm32-rcc";
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clocks-controller;
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#clock-cells = <2>;
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reg = <0x40021000 0x400>;
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label = "STM32_CLK_RCC";
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};
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pinctrl: pin-controller@50000000 {
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compatible = "st,stm32-pinmux";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x50000000 0x2000>;
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gpioa: gpio@50000000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
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label = "GPIOA";
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};
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gpiob: gpio@50000400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
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label = "GPIOB";
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};
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gpioc: gpio@50000800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
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label = "GPIOC";
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};
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gpiod: gpio@50000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
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label = "GPIOD";
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};
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gpiof: gpio@50001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x50001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>;
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label = "GPIOF";
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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status = "disabled";
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label = "TIMERS_3";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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st,prescaler = <10000>;
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label = "PWM_3";
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#pwm-cells = <2>;
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};
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