Andrew Boie d2a72273b7 x86: add support for common page tables ... We provide an option for low-memory systems to use a single set of page tables for all threads. This is only supported if KPTI and SMP are disabled. This configuration saves a considerable amount of RAM, especially if multiple memory domains are used, at a cost of context switching overhead. Some caching techniques are used to reduce the amount of context switch updates; the page tables aren't updated if switching to a supervisor thread, and the page table configuration of the last user thread switched in is cached. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>		2020-11-05 09:33:40 -05:00
..
core
include
zefi
CMakeLists.txt
gen_gdt.py
gen_idt.py
gen_mmu.py
ia32.cmake
intel64.cmake
Kconfig
timing.c