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https://github.com/zephyrproject-rtos/zephyr
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4b411b34a1
Use SOC_SERIES_* for naming SoCs with similar features and architectures with the goal of code reuse. The Series in the config variable should avoid name collisions and clearly denote the relationships within an SoC family. Change-Id: I7a98542f96b5d5dc3acc23782c4d45f98cceb599 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
41 lines
944 B
Plaintext
41 lines
944 B
Plaintext
CONFIG_ARM=y
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CONFIG_BOARD_STM32_MINI_A15=y
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CONFIG_SOC_FAMILY_STM32=y
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CONFIG_SOC_SERIES_STM32F1X=y
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CONFIG_SOC_STM32F103VE=y
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CONFIG_CORTEX_M_SYSTICK=y
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# 72MHz system clock
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
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# enable uart driver
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CONFIG_SERIAL=y
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CONFIG_UART_STM32=y
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CONFIG_UART_STM32_PORT_0=y
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CONFIG_UART_STM32_PORT_0_BAUD_RATE=115200
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# enable pinmux
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CONFIG_PINMUX=y
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CONFIG_PINMUX_STM32=y
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# enable GPIOs
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CONFIG_GPIO=y
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CONFIG_GPIO_STM32=y
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CONFIG_GPIO_STM32_PORTB=y
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# clock configuration
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CONFIG_CLOCK_CONTROL=y
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CONFIG_CLOCK_CONTROL_STM32F10X=y
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CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_PLL=y
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# use on-board 8MHz quartz
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CONFIG_CLOCK_STM32F10X_PLL_SRC_HSE=y
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# produce 72MHz clock at PLL output
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CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER=9
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CONFIG_CLOCK_STM32F10X_AHB_PRESCALER=0
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# APB1 clock must not to exceed 36MHz limit
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CONFIG_CLOCK_STM32F10X_APB1_PRESCALER=2
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CONFIG_CLOCK_STM32F10X_APB2_PRESCALER=0
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# console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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