Cheryl Su 46efefbbe5 soc/riscv: it8xxx2 soc system ... A new platform soc for it8xxx2. Revising the test/kernel/context/src/main.c for it8xxx2 test case. Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>		2020-12-16 08:47:36 -05:00
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arc
arm	soc: stm32h7: define rom offset when using mcuboot	2020-12-14 16:47:05 +01:00
nios2
posix	posix: Add cpu_hold() function to better emulate code delay	2020-12-14 12:32:11 +01:00
riscv	soc/riscv: it8xxx2 soc system	2020-12-16 08:47:36 -05:00
sparc
x86	boards: x86: Add basic documentation for Intel Elkhart Lake	2020-12-12 14:16:23 +02:00
xtensa
Kconfig