Charles E. Youse bd094ddac2 arch/x86: inline x2APIC EOI in 64-bit code ... Like its 32-bit sibling, the 64-bit code should EOI inline rather than invoking a function. Defeats the performance advantages of x2APIC. Signed-off-by: Charles E. Youse <charles.youse@intel.com>		2019-09-23 17:50:09 -07:00
..
arcv2_irq_unit.c	arch: arc: add initial support of ARC TEE	2019-08-10 17:45:22 +02:00
cavs_ictl.c	drivers/interrupt_controller: cavs_ictl: add get_line_state()	2019-09-07 10:20:51 -04:00
cavs_ictl.h
CMakeLists.txt
dw_ictl.c	drivers/interrupt_controller: dw_ictl: add get_line_state()	2019-09-07 10:20:51 -04:00
dw_ictl.h
exti_stm32.c
exti_stm32.h
gic-400.c
ioapic_intr.c
ioapic_priv.h
Kconfig	interrupt: Convert RISC-V plic to use multi-level irq support	2019-09-10 07:34:57 -05:00
Kconfig.multilevel
Kconfig.multilevel.aggregator_template
Kconfig.rv32m1
Kconfig.s1000
Kconfig.sam0
Kconfig.shared_irq
Kconfig.stm32
loapic_intr.c	arch/x86: inline x2APIC EOI in 64-bit code	2019-09-23 17:50:09 -07:00
loapic_spurious.S
plic.c	interrupt: Convert RISC-V plic to use multi-level irq support	2019-09-10 07:34:57 -05:00
rv32m1_intmux.c	drivers/interrupt_controller: rv32m1_intmux: add get_line_state	2019-09-07 10:20:51 -04:00
sam0_eic_priv.h
sam0_eic.c
sam0_eic.h
shared_irq.c
system_apic.c
vexriscv_litex.c