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Update the logic in a corner case, when the target comparator value is one cycle ahead of the counter value. Experiments have shown, that `set_comparator(cyc + 1);` might be not enough in that case, and we still may (rarely) miss the interrupt. This could happen when the counter incremented its value after the `dt` variable was set. As we should set the comparator value two cycles ahead to be on the safe side, increment the target comparator value by 2 instead of 1. Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no> |
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.. | ||
altera_avalon_timer_hal.c | ||
apic_timer.c | ||
arcv2_timer0.c | ||
CMakeLists.txt | ||
cortex_m_systick.c | ||
hpet.c | ||
Kconfig | ||
legacy_api.h | ||
litex_timer.c | ||
loapic_timer.c | ||
mchp_xec_rtos_timer.c | ||
native_posix_timer.c | ||
nrf_rtc_timer.c | ||
riscv_machine_timer.c | ||
rv32m1_lptmr_timer.c | ||
sam0_rtc_timer.c | ||
sys_clock_init.c | ||
xtensa_sys_timer.c |