Andy Ross a8d5437799 soc/xtensa: Misc. checkpatch fixups ... Code style fixes. Kept separate from the original changes to permit easier rebasing. Signed-off-by: Andy Ross <andrew.j.ross@intel.com>		2020-10-21 06:38:53 -04:00
..
arc	arch: arc: Restore MPU registers to its initial states between tests	2020-10-02 11:31:34 +02:00
arm	arch: aarch64: Catch early errors in EL3 and EL1	2020-10-12 12:22:15 -04:00
common	gen_isr_tables: Function ptr instead of (void *)	2020-10-02 18:48:46 +02:00
nios2	benchmarking: remove execution benchmarking code	2020-09-05 13:28:38 -05:00
posix	arch: posix: add missing include for cpuhalt.c	2020-10-20 08:54:59 +02:00
riscv	benchmarking: remove execution benchmarking code	2020-09-05 13:28:38 -05:00
x86	x86: remove NULL check in arch_user_mode_enter	2020-10-20 09:37:49 -07:00
xtensa	soc/xtensa: Misc. checkpatch fixups	2020-10-21 06:38:53 -04:00
CMakeLists.txt
Kconfig	kernel: Add cache coherence management framework	2020-10-21 06:38:53 -04:00